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authorWolfgang Denk <wd@denx.de>2011-04-10 21:24:40 +0200
committerWolfgang Denk <wd@denx.de>2011-04-10 21:24:40 +0200
commit17e967b3dfcc0616a135700a2c39287943ffb958 (patch)
tree5af8e32aefa1073c18e70b3ed048e42b0eac8534 /doc
parent4fd783d63f85871db03b1f06a2572bf43085af32 (diff)
parentc1c087b753633305a0d656a7b4d65d788f4bfb68 (diff)
downloadu-boot-linaro-stable-17e967b3dfcc0616a135700a2c39287943ffb958.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'doc')
-rw-r--r--doc/README.p1022ds24
-rw-r--r--doc/README.p4080ds32
2 files changed, 56 insertions, 0 deletions
diff --git a/doc/README.p1022ds b/doc/README.p1022ds
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+Overview
+--------
+P1022ds is a Low End Dual core platform supporting the P1022 processor
+of QorIQ series. P1022 is an e500 based dual core SOC.
+
+
+Pin Multiplex(hwconfig setting)
+-------------------------------
+Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
+via hwconfig, i.e:
+'setenv hwconfig usb2' to enable USB2 and disable eTsec2
+'setenv hwconfig tdm' to enable TDM and disable Audio
+'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
+ and disable TDM
+'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
+'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
+ is 11MHz), disable eTsec2 and TDM
+
+Warning: TDM and AUDIO can not enable simultaneous !
+and AUDIO codec clock sources only setting as 11MHz or 12MHz !
+'setenv hwconfig 'audclk:12;tdm' --- error !
+'setenv hwconfig 'audclk:11;tdm' --- error !
+'setenv hwconfig 'audclk:10' --- error !
+
diff --git a/doc/README.p4080ds b/doc/README.p4080ds
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+Overview
+--------
+The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC.
+
+SerDes hwconfig configuration
+-----------------------------
+The P4080 RCW includes three sets of bits the specify which SerDes lanes
+should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two),
+and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for
+each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and
+SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered
+down at reset.
+
+To re-enable these banks in U-Boot, two hwconfig are available:
+"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2
+is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into
+SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1'
+indicates that the lane should be powered down.
+
+For example, to indicate that both SerDes banks 2 and 3 are powered down, add
+the following to hwconfig:
+
+ serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf
+
+The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant
+bit corresponds to lane A. To indicate that just lane A of bank 3 is to be
+powered down, use:
+
+ serdes:fsl_srds_lpd_b3=8
+
+These options should be specified only if U-Boot does not automatically power
+on the correct lanes.