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authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2009-03-23 10:22:41 +0100
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2009-03-23 10:22:41 +0100
commit8206bfae3ab7f99965136384360ba2de0c6f4c3b (patch)
treee11bf0fad2e418e6771e8db7dbcb6630a6053f0c /board
parentee1702d75a30d076139d1841383a1fa7220a0e11 (diff)
parent58a518c3d8a2c7de11d414e8b903495daee7dc7e (diff)
downloadu-boot-linaro-stable-8206bfae3ab7f99965136384360ba2de0c6f4c3b.tar.gz
Merge branch 'mimc200'
Diffstat (limited to 'board')
-rw-r--r--board/atmel/atngw100/atngw100.c18
-rw-r--r--board/atmel/atstk1000/Makefile9
-rw-r--r--board/atmel/atstk1000/atstk1000.c15
-rw-r--r--board/atmel/atstk1000/flash.c2
-rw-r--r--board/earthlcd/favr-32-ezkit/favr-32-ezkit.c13
-rw-r--r--board/earthlcd/favr-32-ezkit/flash.c2
-rw-r--r--board/mimc/mimc200/mimc200.c117
-rw-r--r--board/miromico/hammerhead/hammerhead.c26
8 files changed, 87 insertions, 115 deletions
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index fa1a2aa7c..004d8daa9 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -26,6 +26,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/portmux.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,18 +52,18 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
- gpio_enable_macb1();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_ATMEL_SPI)
- gpio_enable_spi0(1 << 0);
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
#endif
return 0;
@@ -88,10 +89,11 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
}
#ifdef CONFIG_CMD_NET
@@ -107,7 +109,7 @@ int board_eth_init(bd_t *bi)
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>
-#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA3
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile
index 155d46ac9..f9b26e5d3 100644
--- a/board/atmel/atstk1000/Makefile
+++ b/board/atmel/atstk1000/Makefile
@@ -24,12 +24,13 @@
include $(TOPDIR)/config.mk
-LIB := $(obj)lib$(BOARD).a
+LIB := $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o
+COBJS-y += $(BOARD).o
+COBJS-y += flash.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
index 94523b5a3..c36cb5717 100644
--- a/board/atmel/atstk1000/atstk1000.c
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -24,8 +24,8 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/portmux.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -78,14 +78,14 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
- gpio_enable_macb1();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
@@ -111,10 +111,11 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x10;
gd->bd->bi_phy_id[1] = 0x11;
+ return 0;
}
#ifdef CONFIG_CMD_NET
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
index 4d380f3fa..0ba06ddc5 100644
--- a/board/atmel/atstk1000/flash.c
+++ b/board/atmel/atstk1000/flash.c
@@ -22,7 +22,7 @@
#include <common.h>
#ifdef CONFIG_ATSTK1000_EXT_FLASH
-#include <asm/cacheflush.h>
+#include <asm/arch/cacheflush.h>
#include <asm/io.h>
#include <asm/sections.h>
diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
index da055899f..8af680fe9 100644
--- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
+++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
@@ -23,8 +23,8 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,13 +50,13 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart3();
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart3(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
@@ -82,9 +82,10 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
}
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c
index 5f73ff04d..0a2614667 100644
--- a/board/earthlcd/favr-32-ezkit/flash.c
+++ b/board/earthlcd/favr-32-ezkit/flash.c
@@ -20,7 +20,7 @@
#include <common.h>
#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
-#include <asm/cacheflush.h>
+#include <asm/arch/cacheflush.h>
#include <asm/io.h>
#include <asm/sections.h>
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
index 8516dcb82..6df741e39 100644
--- a/board/mimc/mimc200/mimc200.c
+++ b/board/mimc/mimc200/mimc200.c
@@ -27,9 +27,10 @@
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
+#include <asm/arch/portmux.h>
#include <lcd.h>
-#define SM_PM_GCCTRL 0x0060
+#include "../../../cpu/at32ap/hsmc3.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -54,98 +55,59 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
-
- /* enable higher address lines for larger flash devices */
- gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */
- gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */
- gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */
-
- /* enable data flash chip select */
- gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */
+ /* Enable 26 address bits and NCS2 */
+ portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
/* de-assert "force sys reset" pin */
- gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */
- gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT);
+ portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
/* init custom i/o */
/* cpu type inputs */
- gpio_select_pio(GPIO_PIN_PE19, 0);
- gpio_select_pio(GPIO_PIN_PE20, 0);
- gpio_select_pio(GPIO_PIN_PE23, 0);
+ portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
+ PORTMUX_DIR_INPUT);
/* main board type inputs */
- gpio_select_pio(GPIO_PIN_PB19, 0);
- gpio_select_pio(GPIO_PIN_PB29, 0);
+ portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
+ PORTMUX_DIR_INPUT);
/* DEBUG input (use weak pullup) */
- gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
+ PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
/* are we suppressing the console ? */
- if (gpio_get_value(GPIO_PIN_PE21) == 1)
- gd->flags |= GD_FLG_SILENT;
+ if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
+ gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
/* reset phys */
- gpio_select_pio(GPIO_PIN_PE24, 0);
- gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */
- gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
-
- /* GCLK0 - 10MHz clock */
- writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
- gpio_select_periph_A(GPIO_PIN_PA30, 0);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
+ portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
udelay(5000);
/* release phys reset */
- gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */
+ gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
+
+ /* setup Data Flash chip select (NCS2) */
+ hsmc3_writel(MODE2, 0x20121003);
+ hsmc3_writel(CYCLE2, 0x000a0009);
+ hsmc3_writel(PULSE2, 0x0a060806);
+ hsmc3_writel(SETUP2, 0x00030102);
+
+ /* setup FRAM chip select (NCS3) */
+ hsmc3_writel(MODE3, 0x10120001);
+ hsmc3_writel(CYCLE3, 0x001e001d);
+ hsmc3_writel(PULSE3, 0x08040704);
+ hsmc3_writel(SETUP3, 0x02050204);
#if defined(CONFIG_MACB)
/* init macb0 pins */
- gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
- gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
- gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
- gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
- gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
- gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
- gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
- gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
- gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
- gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
-#if !defined(CONFIG_RMII)
- gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
- gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
- gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
- gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
- gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
- gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
- gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
- gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
-#endif
-
- /* init macb1 pins */
- gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
- gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
- gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
- gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
- gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
- gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
- gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
- gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
- gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
- gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
-#if !defined(CONFIG_RMII)
- gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
- gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
- gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
- gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
- gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
- gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
- gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
- gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
-#endif
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
@@ -171,10 +133,19 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+int board_postclk_init(void)
+{
+ /* Use GCLK0 as 10MHz output */
+ gclk_enable_output(0, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
+ return 0;
}
/* SPI chip select control */
diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
index d3875f449..8b3e22cd9 100644
--- a/board/miromico/hammerhead/hammerhead.c
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -22,17 +22,15 @@
* MA 02111-1307 USA
*/
-#include "../cpu/at32ap/at32ap700x/sm.h"
-
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/memory-map.h>
+#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -64,14 +62,14 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
@@ -96,18 +94,16 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
}
-void gclk_init(void)
+int board_postclk_init(void)
{
/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
-
- /* Select GCLK3 peripheral function */
- gpio_select_periph_A(GPIO_PIN_PB29, 0);
-
- /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
- sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
+ gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+ return 0;
}