ppc4xx: Big header cleanup, mostly PPC440 related

This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.

This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.

Signed-off-by: Stefan Roese <sr@denx.de>

10 files changed, 26 insertions, 38 deletions

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 41957c9b8..d4205e034 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -554,7 +554,7 @@ void ext_bus_cntlr_init(void)
 	  |
 	  +-------------------------------------------------------------------------*/
 	/* Read Pin Strap Register in PPC440EP */
-	mfsdr(sdr_pstrp0, sdr0_pstrp0);
+	mfsdr(SDR0_PINSTP, sdr0_pstrp0);
 	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 
 	/*-------------------------------------------------------------------------+
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
index 447486297..f2b78a945 100644
--- a/board/amcc/bamboo/bamboo.h
+++ b/board/amcc/bamboo/bamboo.h
@@ -110,17 +110,6 @@
 /*----------------------------------------------------------------------------+
 | SDR Configuration registers
 +----------------------------------------------------------------------------*/
-/* Serial Device Strap Reg 0 */
-#define SDR0_SDSTP0		     0x0020
-/* Serial Device Strap Reg 1 */
-#define SDR0_SDSTP1		     0x0021
-/* Serial Device Strap Reg 2 */
-#define SDR0_SDSTP2		     SDR0_STRP2
-/* Serial Device Strap Reg 3 */
-#define SDR0_SDSTP3		     SDR0_STRP3
-
-#define sdr_pstrp0		     0x0040
-
 #define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
 #define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
 #define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
index 406342fd8..07d185fd2 100644
--- a/board/amcc/bamboo/flash.c
+++ b/board/amcc/bamboo/flash.c
@@ -86,7 +86,7 @@ unsigned long flash_init(void)
 	unsigned long ebc_boot_size;
 	unsigned long boot_selection;
 
-	mfsdr(sdr_pstrp0, val);
+	mfsdr(SDR0_PINSTP, val);
 	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
 
 	if ((index == 5) || (index == 7)) {
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 4338e6bca..c523bca1f 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -321,8 +321,8 @@ int misc_init_r(void)
 	 * This fix will make the MAL burst disabling patch for the Linux
 	 * EMAC driver obsolete.
 	 */
-	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
-	mtdcr(PLB4_ACR, reg);
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
 
 	return 0;
 }
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index fccfaee7b..426321e7b 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -265,8 +265,8 @@ int misc_init_r(void)
 	 * This fix will make the MAL burst disabling patch for the Linux
 	 * EMAC driver obsolete.
 	 */
-	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
-	mtdcr(PLB4_ACR, reg);
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
 
 	/*
 	 * release IO-RST#
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index dd97c7a46..4018a7d29 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -281,7 +281,6 @@ int misc_init_r (void)
 #define PCI0_BRDGOPT1 0x4a
 	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 
-#define PLB0_ACR      0x87
 	/*
 	 * Enable fairness and high bus utilization
 	 */
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index c907b85ae..8238c33c8 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -426,8 +426,8 @@ int misc_init_r(void)
 	 * This fix will make the MAL burst disabling patch for the Linux
 	 * EMAC driver obsolete.
 	 */
-	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
-	mtdcr(PLB4_ACR, reg);
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
 
 #ifdef CONFIG_FPGA
 	pmc440_init_fpga();
diff --git a/board/korat/korat.c b/board/korat/korat.c
index afa36d6c6..4f0513a75 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -553,8 +553,8 @@ int misc_init_r(void)
 	 * This fix will make the MAL burst disabling patch for the Linux
 	 * EMAC driver obsolete.
 	 */
-	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
-	mtdcr(PLB4_ACR, reg);
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
 
 	set_serial_number();
 	set_mac_addresses();
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 0c6f4e571..9622b70d2 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -38,8 +38,8 @@ int board_early_init_f(void)
 	u32 reg;
 
 	/* PLB Write pipelining disabled. Denali Core workaround */
-	mtdcr(PLB0_ACR, 0xDE000000);
-	mtdcr(PLB1_ACR, 0xDE000000);
+	mtdcr(PLB4A0_ACR, 0xDE000000);
+	mtdcr(PLB4A1_ACR, 0xDE000000);
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -249,8 +249,8 @@ int misc_init_r(void)
 	 * This fix will make the MAL burst disabling patch for the Linux
 	 * EMAC driver obsolete.
 	 */
-	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
-	mtdcr(PLB4_ACR, reg);
+	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+	mtdcr(PLB4A0_ACR, reg);
 
 	/*
 	 * Init matrix keyboard
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index b15f99e30..f94d05b08 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -327,7 +327,7 @@ int board_with_pci(void)
 	u32 reg;
 
 	mfsdr(SDR0_PCI0, reg);
-	return (reg & SDR0_XCR_PAE_MASK);
+	return (reg & SDR0_PCI0_PAE_MASK);
 }
 
 /*
@@ -352,28 +352,28 @@ int pci_pre_init(struct pci_controller *hose)
 	 * Set priority for all PLB3 devices to 0.
 	 * Set PLB3 arbiter to fair mode.
 	 */
-	mfsdr(SD0_AMP1, addr);
-	mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB3_ACR);
-	mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
+	mfsdr(SDR0_AMP1, addr);
+	mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(PLB3A0_ACR);
+	mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
 
 	/*
 	 * Set priority for all PLB4 devices to 0.
 	 */
-	mfsdr(SD0_AMP0, addr);
-	mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB4_ACR) | 0xa0000000;	/* Was 0x8---- */
-	mtdcr(PLB4_ACR, addr);  /* Sequoia */
+	mfsdr(SDR0_AMP0, addr);
+	mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(PLB4A0_ACR) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(PLB4A0_ACR, addr);  /* Sequoia */
 
 	/*
 	 * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
 	 * Workaround: Disable write pipelining to DDR SDRAM by setting
-	 * PLB0_ACR[WRP] = 0.
+	 * PLB4A0_ACR[WRP] = 0.
 	 */
-	mtdcr(PLB0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+	mtdcr(PLB4A0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 
 	/* Segment1 */
-	mtdcr(PLB1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+	mtdcr(PLB4A1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 
 	return board_with_pci();
 }