diff options
| author | Stefan Roese <sr@denx.de> | 2009-09-09 16:25:29 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-09-11 10:35:58 +0200 |
| commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
| tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/zeus | |
| parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) | |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/zeus')
| -rw-r--r-- | board/zeus/zeus.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 9bc390f83..fc9dfa02c 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -61,7 +61,7 @@ int board_early_init_f(void) /* * Configure CPC0_PCI to enable PerWE as output */ - mtdcr(cpc0_pci, CPC0_PCI_SPE); + mtdcr(CPC0_PCI, CPC0_PCI_SPE); return 0; } @@ -107,7 +107,7 @@ int misc_init_r(void) /* Re-do sizing to get full correct info */ /* adjust flash start and offset */ - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -135,7 +135,7 @@ int misc_init_r(void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* * Re-check to get correct base address |