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authorStefano Babic <sbabic@denx.de>2012-03-21 00:14:24 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-03-27 22:05:29 +0200
commitc2afbb501c4897c7007711645d300a7156812ad1 (patch)
tree7cb582ab068f89aab0bbef2c824a2be8f0aa8830 /board/teejet
parent61712bcad48d2874fbd9e2dc90255f0885b716b0 (diff)
downloadu-boot-linaro-stable-c2afbb501c4897c7007711645d300a7156812ad1.tar.gz
OMAP3: mt_ventoux: updated timing for FPGA
Fix chipselect timing for FPGA Signed-off-by: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/teejet')
-rw-r--r--board/teejet/mt_ventoux/mt_ventoux.h11
1 files changed, 5 insertions, 6 deletions
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
index 34c1ec5e5..9b2e43ec6 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.h
+++ b/board/teejet/mt_ventoux/mt_ventoux.h
@@ -31,12 +31,11 @@ const omap3_sysinfo sysinfo = {
/* FPGA CS1 configuration */
#define FPGA_GPMC_CONFIG1 0x00001200
-#define FPGA_GPMC_CONFIG2 0x00111a00
-#define FPGA_GPMC_CONFIG3 0x00010100
-#define FPGA_GPMC_CONFIG4 0x06041a04
-#define FPGA_GPMC_CONFIG5 0x0019101a
-#define FPGA_GPMC_CONFIG6 0x890503c0
-#define FPGA_GPMC_CONFIG7 0x00000860
+#define FPGA_GPMC_CONFIG2 0x00161f00
+#define FPGA_GPMC_CONFIG3 0x00040400
+#define FPGA_GPMC_CONFIG4 0x120c1f08
+#define FPGA_GPMC_CONFIG5 0x001e161f
+#define FPGA_GPMC_CONFIG6 0x96080fcf
#define FPGA_BASE_ADDR 0x20000000