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authorMike Frysinger <vapier@gentoo.org>2010-12-23 15:40:12 -0500
committerWolfgang Denk <wd@denx.de>2011-01-09 18:06:50 +0100
commit8ef583a0351590a91394499eb5ca2ab8a703d959 (patch)
tree36dafbd4bdd7e46130aec04bbc0dbfe26e896d9f /board/stx
parent4ffeab2cc00b61bc4616d9e3c25d33937b0feb34 (diff)
miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'board/stx')
-rw-r--r--board/stx/stxgp3/stxgp3.c6
-rw-r--r--board/stx/stxssa/stxssa.c6
-rw-r--r--board/stx/stxxtc/stxxtc.c6
3 files changed, 9 insertions, 9 deletions
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index 25d521170..1ed340efe 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -242,10 +242,10 @@ reset_phy(void)
miiphy_reset("FCC1", 0x0);
/* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+ bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
- bb_miiphy_write(NULL, 0x02, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ bb_miiphy_write(NULL, 0x02, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
#endif /* CONFIG_MII */
#endif
}
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index 1e0acab54..6cd28a34b 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -241,10 +241,10 @@ reset_phy(void)
miiphy_reset("FCC1", 0x0);
/* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+ bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
- bb_miiphy_write(NULL, 0x02, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ bb_miiphy_write(NULL, 0x02, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
#endif /* CONFIG_MII */
#endif
}
diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c
index 6693a7051..4afbbf509 100644
--- a/board/stx/stxxtc/stxxtc.c
+++ b/board/stx/stxxtc/stxxtc.c
@@ -481,12 +481,12 @@ void reset_phys(void)
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read("FEC", phyno, PHY_PHYIDR1, &v);
+ miiphy_read("FEC", phyno, MII_PHYSID1, &v);
if (v == 0xFFFF)
continue;
- miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_POWD);
+ miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
udelay(10000);
- miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+ miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
udelay(10000);
}
}