aboutsummaryrefslogtreecommitdiff
path: root/board/samsung/origen/origen_setup.h
diff options
context:
space:
mode:
authorChander Kashyap <chander.kashyap@linaro.org>2011-12-18 20:16:32 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-02-12 10:11:29 +0100
commit7336278ea286438bc1c71d00eb178b7e085b5c3a (patch)
tree675eed6014de909ddc971f4a4d7c4e894704a0be /board/samsung/origen/origen_setup.h
parentdb68bc2c2de15c6e5066427a2e5024667d886b9a (diff)
downloadu-boot-linaro-stable-7336278ea286438bc1c71d00eb178b7e085b5c3a.tar.gz
Origen: Select SCLKMPLL as FIMD0 parent clock
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/samsung/origen/origen_setup.h')
-rw-r--r--board/samsung/origen/origen_setup.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index d949ad27b..94cccca52 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -56,6 +56,8 @@
#define CLK_SRC_PERIL0_OFFSET 0xC250
#define CLK_DIV_PERIL0_OFFSET 0xC550
+#define CLK_SRC_LCD0_OFFSET 0xC234
+
#define APLL_LOCK_OFFSET 0x14000
#define MPLL_LOCK_OFFSET 0x14008
#define APLL_CON0_OFFSET 0x14100
@@ -351,6 +353,16 @@
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL 6
+#define MDNIE0_SEL_XUSBXTI 1
+#define MDNIE_PWM0_SEL_XUSBXTI 1
+#define MIPI0_SEL_XUSBXTI 1
+#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
+ | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+ | (MDNIE0_SEL_XUSBXTI << 4) \
+ | (FIMD_SEL_SCLKMPLL << 0))
+
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20