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authorAnatolij Gustschin <agust@denx.de>2011-11-19 13:12:11 +0000
committerHeiko Schocher <hs@denx.de>2011-11-23 08:14:27 +0100
commit0a59b7118b1bd26620967c0d1b4addc81835b662 (patch)
tree31389b1d5afadb78a51c62088f8bdd38ed9470bd /board/ronetix
parent67fad9f69d3b96a55282a8f868b7c52397aa5cc3 (diff)
downloadu-boot-linaro-stable-0a59b7118b1bd26620967c0d1b4addc81835b662.tar.gz
board/ronetix/pm9263/pm9263.c: Fix GCC 4.6 warning
Fix: pm9263.c: In function 'pm9263_lcd_hw_psram_init': pm9263.c:167:20: warning: variable 'x' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'board/ronetix')
-rw-r--r--board/ronetix/pm9263/pm9263.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index cfc9847cc..4b6fd663e 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -164,7 +164,6 @@ void lcd_disable(void)
/* Initialize the PSRAM memory */
static int pm9263_lcd_hw_psram_init(void)
{
- volatile uint16_t x;
unsigned long csa;
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
@@ -196,14 +195,14 @@ static int pm9263_lcd_hw_psram_init(void)
at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
/* PSRAM: write BCR */
- x = readw(PSRAM_CTRL_REG);
- x = readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
/* write RCR of the PSRAM */
- x = readw(PSRAM_CTRL_REG);
- x = readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
/* set RCR; 0x10-async mode,0x90-page mode */
writew(0x90, PSRAM_CTRL_REG);
@@ -222,8 +221,8 @@ static int pm9263_lcd_hw_psram_init(void)
at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
/* write RCR of the PSRAM */
- x = readw(PSRAM_CTRL_REG);
- x = readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
/* set RCR;0x10-async mode,0x90-page mode */
writew(0x90, PSRAM_CTRL_REG);