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authorWolfgang Denk <wd@denx.de>2010-08-18 14:14:17 +0200
committerWolfgang Denk <wd@denx.de>2010-10-04 10:58:38 +0200
commitdd09985499ac95484974eb0f832fe47b33369952 (patch)
treeaa8378352b0131db2f90cd3bd991ed4e93826041 /board/manroland/uc100
parentd483a22ecaa44b7c6b3ec98ed0f259c44b5590cb (diff)
downloadu-boot-linaro-stable-dd09985499ac95484974eb0f832fe47b33369952.tar.gz
hmi1001, mucmc52, uc100, uc101: move boards to vendor directory
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Roderik Wildenburg <roderik.wildenburg@manroland.com>
Diffstat (limited to 'board/manroland/uc100')
-rw-r--r--board/manroland/uc100/Makefile45
-rw-r--r--board/manroland/uc100/config.mk29
-rw-r--r--board/manroland/uc100/pcmcia.c198
-rw-r--r--board/manroland/uc100/u-boot.lds140
-rw-r--r--board/manroland/uc100/u-boot.lds.debug134
-rw-r--r--board/manroland/uc100/uc100.c270
6 files changed, 816 insertions, 0 deletions
diff --git a/board/manroland/uc100/Makefile b/board/manroland/uc100/Makefile
new file mode 100644
index 000000000..92ee091f6
--- /dev/null
+++ b/board/manroland/uc100/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+#COBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o pcmcia.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/manroland/uc100/config.mk b/board/manroland/uc100/config.mk
new file mode 100644
index 000000000..a65a8ba2c
--- /dev/null
+++ b/board/manroland/uc100/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# UC100 boards
+#
+
+#TEXT_BASE = 0x40000000
+TEXT_BASE = 0x40700000
diff --git a/board/manroland/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c
new file mode 100644
index 000000000..ad256783c
--- /dev/null
+++ b/board/manroland/uc100/pcmcia.c
@@ -0,0 +1,198 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#ifdef CONFIG_PCMCIA
+
+#define PCMCIA_BOARD_MSG "UC100"
+
+/*
+ * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board.
+ * This leads to board-hangup! (sr, 8 Dez. 2004)
+ */
+static void cfg_ports (void)
+{
+ volatile immap_t *immap;
+
+ immap = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Configure Port A for MAX1602 PC-Card Power-Interface Switch
+ */
+ immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */
+ immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */
+
+ debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n",
+ immap->im_ioport.iop_papar, immap->im_ioport.iop_padir,
+ immap->im_ioport.iop_padat);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ volatile sysconf8xx_t *sysp;
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ immap = (immap_t *)CONFIG_SYS_IMMR;
+ sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+ cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+
+ /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+ cfg_ports ();
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+ if ((reg & mask) == mask) {
+ puts (" 5.0V card found: ");
+ } else {
+ puts (" 3.3V card found: ");
+ }
+
+ /* switch VCC on */
+ immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */
+
+ udelay(10000);
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ volatile immap_t *immap;
+ volatile cpm8xx_t *cp;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ immap = (immap_t *)CONFIG_SYS_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+ /* switch VCC off */
+ immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
+
+ /* Configure PCMCIA General Control Register */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ volatile immap_t *immap;
+ volatile pcmconf8xx_t *pcmp;
+ u_long reg;
+
+ debug ("voltage_set: "
+ PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ immap = (immap_t *)CONFIG_SYS_IMMR;
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn all power pins to Hi-Z
+ */
+ debug ("PCMCIA power OFF\n");
+ cfg_ports (); /* Enables switch, but all in Hi-Z */
+
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(_slot_);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ PCMCIA_PGCRX(_slot_) = reg;
+ udelay(500);
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+ slot+'A');
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA */
diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds
new file mode 100644
index 000000000..0d8f60594
--- /dev/null
+++ b/board/manroland/uc100/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
+ common/dlmalloc.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
+
+ common/env_embedded.o (.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/manroland/uc100/u-boot.lds.debug b/board/manroland/uc100/u-boot.lds.debug
new file mode 100644
index 000000000..a7caa8d90
--- /dev/null
+++ b/board/manroland/uc100/u-boot.lds.debug
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+
+ common/env_embedded.o(.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/manroland/uc100/uc100.c b/board/manroland/uc100/uc100.c
new file mode 100644
index 000000000..bdee4de36
--- /dev/null
+++ b/board/manroland/uc100/uc100.c
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
+/*********************************************************************/
+/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
+/*********************************************************************/
+const uint sdram_init_upm_table[] = {
+ /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
+ /* NOP - Precharge - AutoRefr - NOP - NOP */
+ /* NOP - AutoRefr - NOP */
+ /* NOP - NOP - LoadModeR - NOP - Active */
+ /* Position of Single Read */
+ 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
+ 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
+
+ /* Burst Read. (offset 8 in UPMA RAM) */
+ /* Cycle lent for Initialisation WV */
+ 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Single Write. (offset 18 in UPMA RAM) */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Burst Write. (offset 20 in UPMA RAM) */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Refresh (offset 30 in UPMA RAM) */
+ 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+ 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Exception. (offset 3c in UPMA RAM) */
+ 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+/*********************************************************************/
+/* UPMA initilization table. */
+/*********************************************************************/
+const uint sdram_upm_table[] = {
+ /* single read. (offset 0 in UPMA RAM) */
+ 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
+
+ /* Burst Read. (offset 8 in UPMA RAM) */
+ 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
+ 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Single Write. (offset 18 in UPMA RAM) */
+ 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
+ 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Burst Write. (offset 20 in UPMA RAM) */
+ 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
+ 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Refresh (offset 30 in UPMA RAM) */
+ 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+ 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Exception. (offset 3c in UPMA RAM) */
+ 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
+};
+
+/*********************************************************************/
+/* UPMB initilization table. */
+/*********************************************************************/
+const uint mpm_upm_table[] = {
+ /* single read. (offset 0 in upm RAM) */
+ 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
+ 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* burst read. (Offset 8 in upm RAM) */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* single write. (Offset 0x18 in upm RAM) */
+ 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
+ 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* burst write. (Offset 0x20 in upm RAM) */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Refresh cycle, offset 0x30 */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* Exception, 0ffset 0x3C */
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+
+int board_switch(void)
+{
+ volatile pcmconf8xx_t *pcmp;
+
+ pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+ return ((pcmp->pcmc_pipr >> 24) & 0xf);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming UC100");
+ } else {
+ puts(str);
+ }
+
+ printf (" (SWITCH=%1X)\n", board_switch());
+
+ return 0;
+}
+
+
+/*
+ * Initialize SDRAM
+ */
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ /*---------------------------------------------------------------------*/
+ /* Initialize the UPMA/UPMB registers with the appropriate table. */
+ /*---------------------------------------------------------------------*/
+ upmconfig (UPMA, (uint *) sdram_init_upm_table,
+ sizeof (sdram_init_upm_table) / sizeof (uint));
+ upmconfig (UPMB, (uint *) mpm_upm_table,
+ sizeof (mpm_upm_table) / sizeof (uint));
+
+ /*---------------------------------------------------------------------*/
+ /* Memory Periodic Timer Prescaler: divide by 16 */
+ /*---------------------------------------------------------------------*/
+ memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
+
+ memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
+ memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
+
+ /*---------------------------------------------------------------------*/
+ /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
+ /* for SDRAM */
+ /* */
+ /* NOTE: The refresh rate in MAMR reg is set according to the lowest */
+ /* clock rate (16.67MHz) to allow proper operation for all ADS */
+ /* clock frequencies. */
+ /*---------------------------------------------------------------------*/
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+
+ /*-------------------------------------------------------------------*/
+ /* Wait at least 200 usec for DRAM to stabilize, this magic number */
+ /* obtained from the init code. */
+ /*-------------------------------------------------------------------*/
+ udelay(200);
+
+ memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
+
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+
+ /*---------------------------------------------------------------------*/
+ /* run MRS command in location 5-8 of UPMB. */
+ /*---------------------------------------------------------------------*/
+ memctl->memc_mar = 0x88;
+ /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
+
+ memctl->memc_mcr = 0x80002100;
+ /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
+
+ udelay(200);
+
+ /*---------------------------------------------------------------------*/
+ /* Initialisation for normal access WV */
+ /*---------------------------------------------------------------------*/
+
+ /*---------------------------------------------------------------------*/
+ /* Initialize the UPMA register with the appropriate table. */
+ /*---------------------------------------------------------------------*/
+ upmconfig (UPMA, (uint *) sdram_upm_table,
+ sizeof (sdram_upm_table) / sizeof (uint));
+
+ /*---------------------------------------------------------------------*/
+ /* rerstore MBMR value (4-beat refresh burst.) */
+ /*---------------------------------------------------------------------*/
+ memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
+
+ udelay(200);
+
+ return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
+}
+
+
+int misc_init_r (void)
+{
+ uchar val;
+
+ /*
+ * Make sure that RTC has clock output enabled (triggers watchdog!)
+ */
+ val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
+ val |= 0x80;
+ i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
+
+ /*
+ * Configure PHY to setup LED's correctly and use 100MBit, FD
+ */
+ mii_init();
+
+ /* disable auto-negotiation, 100mbit, full-duplex */
+ fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
+
+ /* set LED's to Link, Transmit, Receive */
+ fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
+
+ return 0;
+}