* Patch by Rune Torgersen, 13 Feb 2003:LABEL_2003_03_06_0200

  Add support for Motorola MPC8266ADS board

* Patch by Kyle Harris, 19 Feb 2003:
  patches for the Intel lubbock board:
  memsetup.S - general cleanup (based on Robert's csb226 code)
  flash.c - overhaul, actually works now
  lubbock.c - fix init funcs to return proper value

* Patch by Kenneth Johansson, 26 Feb 2003:
  - Fixed off by one in RFTA calculation.
  - No need to abort when LDF is lower than we can program it's only
    minimum timing so clamp it to what we can do.
  - Takes function pointer to function for reading the spd_nvram. Usefull
    for faking data or hardcode a module without the nvram.
  - fix other user for above change
  - fix some comments.

* Patches by Brian Waite, 26 Feb 2003:
  - fix port for evb64260 board
  - fix PCI for evb64260 board
  - fix PCI scan

* Patch by Reinhard Meyer, 1 Mar 2003:
  Add support for EMK TOP860 Module

* Patch by Yuli Barcohen, 02 Mar 2003:
  Add SPD EEPROM support for MPC8260ADS board

4 files changed, 435 insertions, 712 deletions

diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk
index d6ec08cf1..0ffe1ba63 100644
--- a/board/lubbock/config.mk
+++ b/board/lubbock/config.mk
@@ -1,12 +1,3 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-
 #TEXT_BASE = 0xa1700000
 TEXT_BASE = 0xa3000000
 #TEXT_BASE = 0
diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c
index 84c09a853..a93875083 100644
--- a/board/lubbock/flash.c
+++ b/board/lubbock/flash.c
@@ -1,10 +1,9 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2001
  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,46 +25,62 @@
  */
 
 #include <common.h>
+#include <linux/byteorder/swab.h>
 
-#define FLASH_BANK_SIZE 0x2000000
-#define MAIN_SECT_SIZE  0x40000         /* 2x16 = 256k per sector */
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
 
 /*-----------------------------------------------------------------------
+ * Functions
  */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+void inline  spin_wheel(void);
 
-ulong flash_init(void)
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
 {
-    int i, j;
+   int i;
     ulong size = 0;
 
     for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
     {
-	ulong flashbase = 0;
-	flash_info[i].flash_id =
-	  (INTEL_MANUFACT & FLASH_VENDMASK) |
-	  (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
         switch (i)
         {
            case 0:
-	        flashbase = PHYS_FLASH_1;
+            flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]);
+	         flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
                 break;
            case 1:
-	        flashbase = PHYS_FLASH_2;
+            flash_get_size((FPW *)PHYS_FLASH_2, &flash_info[i]);
+	         flash_get_offsets(PHYS_FLASH_2, &flash_info[i]);
                 break;
            default:
 	        panic("configured to many flash banks!\n");
                 break;
         }
-	for (j = 0; j < flash_info[i].sector_count; j++)
-	{
-	    flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
-	}
 	size += flash_info[i].size;
     }
 
@@ -86,71 +101,140 @@ ulong flash_init(void)
 
 /*-----------------------------------------------------------------------
  */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
 void flash_print_info  (flash_info_t *info)
 {
-    int i, j;
+	int i;
 
-    for (j=0; j<CFG_MAX_FLASH_BANKS; j++)
-    {
-        switch (info->flash_id & FLASH_VENDMASK)
-        {
-        case (INTEL_MANUFACT & FLASH_VENDMASK):
-	        printf("Intel: ");
-	        break;
-        default:
-	        printf("Unknown Vendor ");
-	        break;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
         }
 
-        switch (info->flash_id & FLASH_TYPEMASK)
-        {
-        case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-	        printf("28F128J3 (128Mbit)\n");
-	        break;
-        default:
-	        printf("Unknown Chip Type\n");
-	        goto Done;
-	        break;
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F128J3A:
+				printf ("28F128J3A\n"); break;
+	default:		printf ("Unknown Chip Type\n"); break;
         }
 
-        printf("  Size: %ld MB in %d Sectors\n",
+	printf ("  Size: %ld MB in %d Sectors\n",
 	        info->size >> 20, info->sector_count);
 
-        printf("  Sector Start Addresses:");
-        for (i = 0; i < info->sector_count; i++)
-        {
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
 	        if ((i % 5) == 0)
-	        {
 	        printf ("\n   ");
-	        }
-	        printf (" %08lX%s", info->start[i],
-		        info->protect[i] ? " (RO)" : "     ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
         }
         printf ("\n");
-        info++;
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0x00AA00AA;
+	addr[0x2AAA] = (FPW)0x00550055;
+	addr[0x5555] = (FPW)0x00900090;
+
+   mb();
+	value = addr[0];
+
+   switch (value) {
+
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+   mb();
+	value = addr[1];			/* device ID		*/
+
+   switch (value) {
+
+   case (FPW)INTEL_ID_28F128J3A:
+      info->flash_id += FLASH_28F128J3A;
+      info->sector_count = 128;
+      info->size = 0x02000000;
+      break;            /* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
     }
 
-Done:
+	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+
+	return (info->size);
 }
 
+
 /*-----------------------------------------------------------------------
  */
 
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
     int flag, prot, sect;
-    int rc = ERR_OK;
-
-    if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
+	ulong type, start, now, last;
+	int rcode = 0;
 
     if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
     }
 
-    if ((info->flash_id & FLASH_VENDMASK) !=
-	(INTEL_MANUFACT & FLASH_VENDMASK)) {
-	return ERR_UNKNOWN_FLASH_VENDOR;
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
     }
 
     prot = 0;
@@ -159,153 +243,79 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	    prot++;
 	}
     }
-    if (prot)
-	return ERR_PROTECTED;
 
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+   /* Disable interrupts which might cause a timeout here */
     flag = disable_interrupts();
 
     /* Start erase on unprotected sectors */
-    for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
 
 	printf("Erasing sector %2d ... ", sect);
 
 	/* arm simple, non interrupt dependent timer */
 	reset_timer_masked();
 
-	if (info->protect[sect] == 0) {	/* not protected */
-	    vu_short *addr = (vu_short *)(info->start[sect]);
+			*addr = (FPW)0x00500050;	/* clear status register */
+			*addr = (FPW)0x00200020;	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
 
-	    *addr = 0x20;	/* erase setup */
-	    *addr = 0xD0;	/* erase confirm */
-
-	    while ((*addr & 0x80) != 0x80) {
+			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
 		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
-		    *addr = 0xB0; /* suspend erase */
-		    *addr = 0xFF;	/* reset to read mode */
-		    rc = ERR_TIMOUT;
-		    goto outahere;
-		}
-	    }
-
-	    /* clear status register command */
-	    *addr = 0x50;
-	    /* reset to read mode */
-	    *addr = 0xFF;
+					printf ("Timeout\n");
+					*addr = (FPW)0x00B000B0; /* suspend erase	  */
+					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					rcode = 1;
+					break;
 	}
-	printf("ok.\n");
     }
-    if (ctrlc())
-      printf("User Interrupt!\n");
 
-outahere:
+			*addr = 0x00500050; /* clear status register cmd.   */
+			*addr = 0x00FF00FF; /* resest to read mode          */
 
-    /* allow flash to settle - wait 10 ms */
-    udelay_masked(10000);
-
-    if (flag)
-      enable_interrupts();
-
-    return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash
- */
-
-static int write_word (flash_info_t *info, ulong dest, ushort data)
-{
-    vu_short *addr = (vu_short *)dest, val;
-    int rc = ERR_OK;
-    int flag;
-
-    /* Check if Flash is (sufficiently) erased
-     */
-    if ((*addr & data) != data)
-        return ERR_NOT_ERASED;
-
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    flag = disable_interrupts();
-
-    /* clear status register command */
-    *addr = 0x50;
-
-    /* program set-up command */
-    *addr = 0x40;
-
-    /* latch address/data */
-    *addr = data;
-
-    /* arm simple, non interrupt dependent timer */
-    reset_timer_masked();
-
-    /* wait while polling the status register */
-    while(((val = *addr) & 0x80) != 0x80)
-    {
-	if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
-	    rc = ERR_TIMOUT;
-	    /* suspend program command */
-	    *addr = 0xB0;
-	    goto outahere;
-	}
-    }
-
-    if(val & 0x1A) {	/* check for error */
-        printf("\nFlash write error %02x at address %08lx\n",
-    	   (int)val, (unsigned long)dest);
-        if(val & (1<<3)) {
-	    printf("Voltage range error.\n");
-	    rc = ERR_PROG_ERROR;
-	    goto outahere;
+			printf (" done\n");
         }
-        if(val & (1<<1)) {
-	    printf("Device protect error.\n");
-	    rc = ERR_PROTECTED;
-	    goto outahere;
         }
-        if(val & (1<<4)) {
-	    printf("Programming error.\n");
-	    rc = ERR_PROG_ERROR;
-	    goto outahere;
-        }
-        rc = ERR_PROG_ERROR;
-        goto outahere;
-    }
-
-outahere:
-    /* read array command */
-    *addr = 0xFF;
-
-    if (flag)
-      enable_interrupts();
-
-    return rc;
+	return rcode;
 }
 
 /*-----------------------------------------------------------------------
- * Copy memory to flash.
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
  */
 
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
     ulong cp, wp;
-    ushort data;
-    int l;
-    int i, rc;
+	FPW data;
+	int count, i, l, rc, port_width;
 
-    wp = (addr & ~1);	/* get lower word aligned address */
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
 
     /*
      * handle unaligned start bytes
@@ -313,51 +323,110 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
     if ((l = addr - wp) != 0) {
 	data = 0;
 	for (i=0, cp=wp; i<l; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 8);
+			data = (data << 8) | (*(uchar *)cp);
 	}
-	for (; i<2 && cnt>0; ++i) {
-	    data = (data >> 8) | (*src++ << 8);
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
 	    --cnt;
 	    ++cp;
 	}
-	for (; cnt==0 && i<2; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 8);
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
 	}
 
-	if ((rc = write_word(info, wp, data)) != 0) {
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
 	    return (rc);
 	}
-	wp += 2;
+		wp += port_width;
     }
 
     /*
      * handle word aligned part
      */
-    while (cnt >= 2) {
-	data = *((vu_short*)src);
-	if ((rc = write_word(info, wp, data)) != 0) {
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
 	    return (rc);
 	}
-	src += 2;
-	wp  += 2;
-	cnt -= 2;
+		wp  += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800)
+		{
+         spin_wheel();
+			count = 0;
+		}
     }
 
     if (cnt == 0) {
-	return ERR_OK;
+		return (0);
     }
 
     /*
      * handle unaligned tail bytes
      */
     data = 0;
-    for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-	data = (data >> 8) | (*src++ << 8);
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
 	--cnt;
     }
-    for (; i<2; ++i, ++cp) {
-	data = (data >> 8) | (*(uchar *)cp << 8);
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
     }
 
-    return write_word(info, wp, data);
+	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+   static int r=0,p=0;
+   static char w[] = "\\/-";
+
+   printf("\010%c", w[p]);
+   (++p == 3) ? (p = 0) : 0;
 }
+
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index ba9b86b31..2487a4cba 100644
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -47,7 +47,7 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa0000100;
 
-	return 1;
+	return 0;
 }
 
 int dram_init (void)
@@ -62,6 +62,6 @@ int dram_init (void)
 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-	return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE +
-			PHYS_SDRAM_4_SIZE;
+
+   return 0;
 }
diff --git a/board/lubbock/memsetup.S b/board/lubbock/memsetup.S
index c0278340a..5bbd85958 100644
--- a/board/lubbock/memsetup.S
+++ b/board/lubbock/memsetup.S
@@ -39,12 +39,16 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
    .endm
 
 
+/*
+ * 	Memory setup
+ */
+
 .globl memsetup
 memsetup:
 
     mov      r10, lr
 
-    /* Set up GPIO pins first */
+	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
 	ldr		r1,	=CFG_GPSR0_VAL
@@ -106,562 +110,284 @@ memsetup:
 	ldr		r1,	=CFG_GAFR2_U_VAL
 	str		r1,   [r0]
 
-   /* enable GPIO pins */
-	ldr		r0,	=PSSR
+	ldr	r0,	=PSSR		/* enable GPIO pins */
 	ldr		r1,	=CFG_PSSR_VAL
 	str		r1,   [r0]
 
-   ldr    r3, =MSC1		    		/* low - bank 2 Lubbock Registers / SRAM */
-   ldr    r2, =CFG_MSC1_VAL			/* high - bank 3 Ethernet Controller */
-   str    r2, [r3]  				/* need to set MSC1 before trying to write to the HEX LEDs */
-   ldr    r2, [r3]  				/* need to read it back to make sure the value latches (see MSC section of manual) */
-
-   ldr    r1, =LED_BLANK
-   mov    r0, #0xFF
-   str    r0, [r1]    		/* turn on hex leds */
-
-loop:
-   ldr		r0, =0xB0070001
-   ldr    	r1, =_LED
-   str    	r0, [r1]    							/* hex display */
-
-/*********************************************************************
-    Initlialize Memory Controller
-	 The sequence below is based on the recommended init steps detailed
-	 in the EAS, chapter 5 (Chapter 10, Operating Systems Developers Guide)
-
-
-    pause for 200 uSecs- allow internal clocks to settle
-	 *Note: only need this if hard reset... doing it anyway for now
-*/
-
-	@ ---- Wait 200 usec
-	ldr r3, =OSCR       @ reset the OS Timer Count to zero
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
 	mov r2, #0
 	str r2, [r3]
-	ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
 1:
 	ldr r2, [r3]
 	cmp r4, r2
 	bgt 1b
 
 mem_init:
-        @ get memory controller base address
-        ldr     r1,  =MEMC_BASE
 
-@****************************************************************************
-@  Step 1
-@
+        ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
 
-        @ write msc0, read back to ensure data latches
-        @
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+        /* MSC0: nCS(0,1)                                                   */
         ldr     r2,   =CFG_MSC0_VAL
         str     r2,   [r1, #MSC0_OFFSET]
-        ldr     r2,   [r1, #MSC0_OFFSET]
-
-        @ write msc1
+        ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+        /* MSC1: nCS(2,3)                                                   */
         ldr     r2,  =CFG_MSC1_VAL
         str     r2,  [r1, #MSC1_OFFSET]
         ldr     r2,  [r1, #MSC1_OFFSET]
 
-        @ write msc2
+	/* MSC2: nCS(4,5)                                                   */
         ldr     r2,  =CFG_MSC2_VAL
         str     r2,  [r1, #MSC2_OFFSET]
         ldr     r2,  [r1, #MSC2_OFFSET]
 
-        @ write mecr
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
         ldr     r2,  =CFG_MECR_VAL
         str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
 
-        @ write mcmem0
+	/* MCMEM0: Card Interface slot 0 timing                             */
         ldr     r2,  =CFG_MCMEM0_VAL
         str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
-        @ write mcmem1
+        /* MCMEM1: Card Interface slot 1 timing                             */
         ldr     r2,  =CFG_MCMEM1_VAL
         str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
-        @ write mcatt0
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
         ldr     r2,  =CFG_MCATT0_VAL
         str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
 
-        @ write mcatt1
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
         ldr     r2,  =CFG_MCATT1_VAL
         str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
 
-        @ write mcio0
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
         ldr     r2,  =CFG_MCIO0_VAL
         str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
 
-        @ write mcio1
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
         ldr     r2,  =CFG_MCIO1_VAL
         str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
 
-        @-------------------------------------------------------
-        @ 3rd bullet, Step 1
-        @
+	/* ---------------------------------------------------------------- */
+        /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+        /* ---------------------------------------------------------------- */
 
-        @ get the mdrefr settings
-        ldr     r3,  =CFG_MDREFR_VAL_100
 
-        @ extract DRI field (we need a valid DRI field)
-        @
-        ldr     r2,  =0xFFF
+	/* ---------------------------------------------------------------- */
+        /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+        /* ---------------------------------------------------------------- */
 
-        @ valid DRI field in r3
-        @
-        and     r3,  r3,  r2
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
 
-        @ get the reset state of MDREFR
-        @
+        ldr     r3,     =CFG_MDREFR_VAL
+        ldr     r2,     =0xFFF
+        and     r3,     r3,  r2
+	ldr	r4,	=0x03ca4000
+        orr     r4,     r4,  r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
         ldr     r4,  [r1, #MDREFR_OFFSET]
 
-        @ clear the DRI field
-        @
-        bic     r4,  r4,  r2
-
-        @ insert the valid DRI field loaded above
-        @
-        orr     r4,  r4,  r3
-
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
-
-        @ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@  Step 2
-@
-        /* This should be for SRAM, why is it commented out??? */
-
-        @ fetch sxcnfg value
-        @
-        @ldr     r2,  =0
-        @ write back sxcnfg
-        @str     r2,  [r1, #SXCNFG_OFFSET]
-
-/*        @if sxcnfg=0, don't program for synch-static memory */
-        @cmp     r2,  #0
-        @beq     1f
-
-        @program sxmrs
-        @ldr     r2,  =SXMRS_SETTINGS
-        @str     r2,  [r1, #SXMRS_OFFSET]
-
-
-@****************************************************************************
-@  Step 3
-@
-
-        @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-        @ clear the free-running clock bits
-        @ (clear K0Free, K1Free, K2Free
-        @
-        bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-        @ set K1RUN if bank 0 installed
-        @
-        orr   r4,  r4,  #0x00010000
-
-
-
-#ifdef THIS
-@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-@<!<!<!<!<!<!<!<!<!<!<!  Begin INSERT 1    <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-        @ Lubbock: Allow the user to select the {T/R/M} with predetermined
-        @   SDCLK.  Based on Table 3-1 in PXA250 and PXA210 Dev Man.
-        @
-        @  * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
-        @
-        @   S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)
-        @   S25, S26 used to provide all 200 MHz BIN values for Sabinal
-        @
-        @   S23: Force the halving of MemClk when deriving SDCLK[1]
-        @        DOT: no override  !DOT: halve (if not already forced half)
-/*        @        *For certain MemClks, SDCLK's derivation is forced to be halved */
-        @
-        @   S24: Run/Turbo.
-        @        DOT: Run mode   !DOT: Turbo mode
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-        @
-        @ Allow the user to control K1DB2 where applicable
-        @
-        @ Get the value of S23:          @ 1 = DOT (unity), 0 = !DOT (halve it)
-        @
-        @ DOT:   set K1DB2     (SDCLD = MemClk)
-        @ !DOT:  clear K1DB2   (SDCLK = MemClk/2)
-        @
-        @ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-        bl GET_S23                          @ r3, r2                    @ get the value of S23 in R0, i put the base adx of fpga in r3
-
-        cmp      r3, #0x0                 @ is !DOT?
-        orreq    r4, r4,  #0x00020000     @ SDClk[1] = MemClk/2
-        bicne    r4, r4,  #0x00020000     @ SDClk[1] = MemClk
-
-        @
-        @ Next, we need to look for S25,S26 selections that necessitate the
-        @  halving of MemClk to derive SDCLK[1]: (S25,S26)={03-0C, 10-13}
-        @ Override above S23-based selection accordingly.
-        @
-        ldr r2, =FPGA_REGS_BASE_PHYSICAL
-        bl  GET_S25                           @ r0, r2
-                                       @ get the value of S25 in R0, i put the base adx of fpga in r2
-
-
-
-        ldr r2, =FPGA_REGS_BASE_PHYSICAL
-        BL  GET_S26                              @ r3, r2
-                                      @ get the value of S26 in R1, i put the base adx of fpga in r2
-
-        orr     r0, r0, r3               @ concatenate S25 & S26 vals
-        and     r0, r0, #0xFF
-
-        @ Set K1DB2 for the frequencies that require it
-        @
-        cmp     r0, #0x03
-        cmpne   r0, #0x04
-        cmpne   r0, #0x05
-        cmpne   r0, #0x06
-        cmpne   r0, #0x07
-        cmpne   r0, #0x08
-        cmpne   r0, #0x09
-        cmpne   r0, #0x0A
-        cmpne   r0, #0x0B
-        cmpne   r0, #0x0C
-        cmpne   r0, #0x10
-        cmpne   r0, #0x11
-        cmpne   r0, #0x12
-        cmpne   r0, #0x13
-        orreq   r4, r4,  #0x00020000     @ SDCLK[1] = (MemClk)/2 for 03 - 0C @ 10 - 13
-
-        @
-        @ *Must make MSC0&1 adjustments now for MEMClks > 100MHz.
-        @
-        @ Adjust MSC0 for MemClks > 100 MHz
-        @
-        ldreq   r0,   [r1, #MSC0_OFFSET]
-        ldreq   r3,   =0x7F007F00
-        biceq   r0,   r0, r3                @ clear MSC0[14:12, 11:8] (RRR, RDN)
-        ldreq   r3,   =0x46004600
-        orreq   r0,   r0, r3                @ set   MSC0[14, 10:9]  (doubling RRR, RDN)
-        streq   r0,   [r1, #MSC0_OFFSET]
-        ldreq   r0,   [r1, #MSC0_OFFSET]    @ read it back to ensure that the data latches
-
-        @
-        @ Adjust MSC1.LH for MemClks > 100 MHz
-        @
-        ldreq   r0,   [r1, #MSC1_OFFSET]
-        ldreq   r3,   =0x7FF0
-        biceq   r0,   r0, r3               @ clear MSC1[14:12, 11:8, 7:4] (RRR, RDN, RDF)
-        ldreq   r3,   =0x4880
-        orreq   r0,   r0, r3               @ set   MSC1[14, 11, 7]  (doubling RRR, RDN, RDF)
-        streq   r0,   [r1, #MSC1_OFFSET]
-        ldreq   r0,   [r1, #MSC1_OFFSET]   @ read it back to ensure that the data latches
-
-        @                                                                   @
-        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-#endif
+        /* Note: preserve the mdrefr value in r4                            */
 
-@<!<!<!<!<!<!<!<!<!<!<!    End INSERT 1    <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
-@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
 
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
-        ldr     r4,  [r1, #MDREFR_OFFSET]
+	/* Initialize SXCNFG register. Assert the enable bits               */
 
-        @ deassert SLFRSH
-        @
-        bic     r4,  r4,  #0x00400000
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
+	/* FIXME: we use async mode for now                                 */
 
-        @ assert E1PIN
-        @
-        orr     r4,  r4,  #0x00008000
 
-        @ write back mdrefr
-        @
-        str     r4,  [r1, #MDREFR_OFFSET]
+        /* ---------------------------------------------------------------- */
+        /* Step 4: Initialize SDRAM                                         */
+        /* ---------------------------------------------------------------- */
+
+        /* set MDREFR according to user define with exception of a few bits */
+
+        ldr     r4,     =CFG_MDREFR_VAL
+	orr	r4,	r4,	#(MDREFR_SLFRSH)
+	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
         ldr     r4,  [r1, #MDREFR_OFFSET]
-        nop
-        nop
 
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
 
-@****************************************************************************
-@  Step 4
-@
+	bic	r4,	r4,	#(MDREFR_SLFRSH)
+        str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+        ldr     r4,  [r1, #MDREFR_OFFSET]
 
-        @ fetch platform value of mdcnfg
-        @
-        ldr     r2,  =CFG_MDCNFG_VAL
 
-        @ disable all sdram banks
-        @
-        bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-        bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
 
-        @ program banks 0/1 for bus width
-        @
-        bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
+        ldr     r4,     =CFG_MDREFR_VAL
+        str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+        ldr     r4,     [r1, #MDREFR_OFFSET]
 
 
-        @ write initial value of mdcnfg, w/o enabling sdram banks
-        @
-        str     r2,  [r1, #MDCNFG_OFFSET]
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
 
-@ ****************************************************************************
-@  Step 5
-@
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
-        @ pause for 200 uSecs
-        @
-    	ldr r3, =OSCR   @reset the OS Timer Count to zero
+        str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+        ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
     	mov r2, #0
 	    str r2, [r3]
-	    ldr r4, =0x300			@really 0x2E1 is about 200usec, so 0x300 should be plenty
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
 1:
 	    ldr r2, [r3]
 	    cmp r4, r2
 	    bgt 1b
 
 
-@****************************************************************************
-@  Step 6
-@
-
-	    mov    r0, #0x78				    @turn everything off
-      mcr    p15, 0, r0, c1, c0, 0		@(caches off, MMU off, etc.)
-
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
 
-@ ****************************************************************************
-@  Step 7
-@
-        @ Access memory *not yet enabled* for CBR refresh cycles (8)
-        @ - CBR is generated for all banks
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
 
-	    ldr     r2, =CFG_DRAM_BASE
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
 
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
 
-@ ****************************************************************************
-@  Step 8: NOP (enable dcache if you wanna... we dont)
-@
-
-
-@ ****************************************************************************
-@  Step 9
-@
-
-
-        @get memory controller base address
-        @
-        ldr     r1,  =MEMC_BASE
-
-        @fetch current mdcnfg value
-        @
         ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-        @enable sdram bank 0 if installed (must do for any populated bank)
-        @
-        orr     r3,  r3,  #MDCNFG_DE0
-
-        @write back mdcnfg, enabling the sdram bank(s)
-        @
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
         str     r3,  [r1, #MDCNFG_OFFSET]
 
+	/* Step 4h: Write MDMRS.                                            */
 
-@****************************************************************************
-@  Step 10
-@
-
-        @ write mdmrs
-        @
         ldr     r2,  =CFG_MDMRS_VAL
         str     r2,  [r1, #MDMRS_OFFSET]
 
 
-@****************************************************************************
-@  Step 11: Final Step
-@
+	/* We are finished with Intel's memory controller initialisation    */
+
 
-@INITINTC
-        @********************************************************************
-        @ Disable (mask) all interrupts at the interrupt controller
-        @
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
 
-        @ clear the interrupt level register (use IRQ, not FIQ)
-        @
-        mov     r1, #0
+initirqs:
+
+        mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
         ldr     r2,  =ICLR
         str     r1,  [r2]
 
-        @ mask all interrupts at the controller
-        @
-        ldr     r2,  =ICMR
+        ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
         str     r1,  [r2]
 
 
-@INITCLKS
-        @ ********************************************************************
-        @ Disable the peripheral clocks, and set the core clock
-        @ frequency (hard-coding at 398.12MHz for now).
-        @
+        /* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+        /* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
 
-		@ Turn Off ALL on-chip peripheral clocks for re-configuration
-		@ *Note: See label 'ENABLECLKS' for the re-enabling
-		@
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
         ldr     r1,  =CKEN
         mov     r2,  #0
         str     r2,  [r1]
 
 
-        @ default value in case no valid rotary switch setting is found
-        ldr     r2, =(CCCR_L27 | CCCR_M2 | CCCR_N10)        @ DEFAULT: {200/200/100}
+        /* default value in case no valid rotary switch setting is found    */
+        ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
 
-
-        @... and write the core clock config register
-        @
+        /* ... and write the core clock config register                     */
         ldr     r1,  =CCCR
         str     r2,  [r1]
 
-/*        @ enable the 32Khz oscillator for RTC and PowerManager
-        @
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
         ldr     r1,  =OSCC
         mov     r2,  #OSCC_OON
         str     r2,  [r1]
 
-
-        @ NOTE:  spin here until OSCC.OOK get set,
-        @        meaning the PLL has settled.
-        @
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
 60:
         ldr     r2, [r1]
         ands    r2, r2, #1
         beq     60b
-*/
-
-@OSCC_OON_DONE
-
-
-#ifdef  A0_COTULLA
-    @****************************************************************************
-    @ !!! Take care of A0 Errata Sighting #4 --
-    @ after a frequency change, the memory controller must be restarted
-    @
-
-        @ get memory controller base address
-        ldr     r1,  =MEMC_BASE
-
-        @ get the current state of MDREFR
-        @
-        ldr     r2,  [r1, #MDREFR_OFFSET]
-
-        @ clear E0PIN, E1PIN
-        @
-        bic     r3,  r2,  #(MDREFR_E0PIN | MDREFR_E1PIN)
-
-        @ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
-        @
-        str     r3,  [r1, #MDREFR_OFFSET]
-
-        @ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
-        @
-        str     r2,  [r1, #MDREFR_OFFSET]
-
-        @ get the current state of MDCNFG
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ disable all SDRAM banks
-        @
-        bic     r3,  r3,  #(MDCNFG_DE0 | MDCNFG_DE1)
-        bic     r3,  r3,  #(MDCNFG_DE2 |  MDCNFG_DE3)
-
-        @ write back MDCNFG
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-	    @ Access memory not yet enabled for CBR refresh cycles (8)
-        @ - CBR is generated for *all* banks
-	    ldr     r2, =CFG_DRAM_BASE
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-	    str     r2, [r2]
-
-        @ fetch current mdcnfg value
-        @
-        ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ enable sdram bank 0 if installed
-        @
-        orr     r3,  r3,  #MDCNFG_DE0
-
-        @ write back mdcnfg, enabling the sdram bank(s)
-        @
-        str     r3,  [r1, #MDCNFG_OFFSET]
-
-        @ write mdmrs
-        @
-        ldr     r2,  =CFG_MDMRS_VAL
-        str     r2,  [r1, #MDMRS_OFFSET]
-
-
-
-    /*    @ errata: don't enable auto power-down */
-        @ get current value of mdrefr
-        @ldr     r3,  [r1, #MDREFR_OFFSET]
-        @ enable auto-power down
-        @orr     r3,  r3,  #MDREFR_APD
-        @write back mdrefr
-        @str     r3,  [r1, #MDREFR_OFFSET]
-
-#endif A0_Cotulla
-
-
-  ldr     r0, =0x000C0dE3
-  ldr    	r1, =_LED
-  str    	r0, [r1]    		/* hex display */
-
-@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
-@ ^%^%^%^%^%^%^%^%^%   above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
-@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
+#endif
 
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+        /* ---------------------------------------------------------------- */
 
 	/* Save SDRAM size */
     ldr     r1, =DRAM_SIZE
 	 str	   r8, [r1]
 
-    ldr     r0, =0xC0DE0006
-    ldr    	r1, =_LED
-    str    	r0, [r1]    		/* hex display */
-
-	/* Interrupt init */
-	/* Mask all interrupts */
+	/* Interrupt init: Mask all interrupts                              */
     ldr	r0, =ICMR /* enable no sources */
 	mov r1, #0
     str r1, [r0]
 
+	/* FIXME */
+
 #define NODEBUG
 #ifdef NODEBUG
 	/*Disable software and data breakpoints */
@@ -676,74 +402,11 @@ mem_init:
 
 #endif
 
-	ldr     r0, =0xBEEF001D
-    ldr    	r1, =_LED
-    str    	r0, [r1]    		/* hex display */
+        /* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+        /* ---------------------------------------------------------------- */
 
-	mov	pc, r10
-
-@ End memsetup
-
-@ %%%%%%%%%%%   Useful subroutines
-GET_S23:
-    @ This macro will read S23 and return its value in r3
-    @ r2 contains the base address of the Lubbock user registers
-    ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-    /*@ read S23's value */
-    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r3, r3, #0x200
-
-    @ get bit into position 0
-    mov     r3, r3, LSR #9
-
-    mov     pc, lr
-@ End GET_S23
-
-
-GET_S24:
-    @ This macro will read S24 and return its value in r0
-    @ r2 contains the base address of the Lubbock user registers
-    ldr r2, =FPGA_REGS_BASE_PHYSICAL
-
-    /*@ read S24's value */
-    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r0, r0, #0x100
-
-    @ get bit into position 0
-    mov     r0, r0, LSR #8
+endmemsetup:
 
     mov     pc, lr
-@ End GET_S23
-
-
-GET_S25:
-    @ This macro will read rotary S25 and return its value in r0
-    @ r2 contains the base address of the Lubbock user registers
-    @ read the user switches register
-    ldr     r0, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r0, r0, #0xF0
-
-    mov     pc, lr
-@ End subroutine
-
-
-GET_S26:
-    @ This macro will read rotary S26 and return its value in r3
-    @ r2 contains the base address of the Lubbock user registers
-    @ read the user switches register
-    ldr     r3, [r2, #USER_SWITCHES_OFFSET]
-
-    @ mask out irrelevant bits
-    and     r3, r3, #0x0F
-
-    mov     pc, lr
-@ End subroutine GET_S26
-