imx27lite: add support for imx27lite board from LogicPD

This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Wolfgang Denk <wd@denx.de>

4 files changed, 295 insertions, 0 deletions

diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
new file mode 100644
index 000000000..c404cef58
--- /dev/null
+++ b/board/logicpd/imx27lite/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= imx27lite.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/board/logicpd/imx27lite/config.mk b/board/logicpd/imx27lite/config.mk
new file mode 100644
index 000000000..a2e7768dd
--- /dev/null
+++ b/board/logicpd/imx27lite/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xA7F00000
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
new file mode 100644
index 000000000..63375d5da
--- /dev/null
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+
+	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_MXC_UART
+	mx27_uart_init_pins();
+#endif
+#ifdef CONFIG_FEC_MXC
+	mx27_fec_init_pins();
+	imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
+	writel(readl(&regs->port[PORTC].dr) | (1 << 31),
+				&regs->port[PORTC].dr);
+#endif
+#ifdef CONFIG_MXC_MMC
+	mx27_sd2_init_pins();
+#endif
+
+	return 0;
+}
+
+int dram_init (void)
+{
+
+#if CONFIG_NR_DRAM_BANKS > 0
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+#endif
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("LogicPD imx27lite\n");
+	return 0;
+}
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
new file mode 100644
index 000000000..e2cdecb96
--- /dev/null
+++ b/board/logicpd/imx27lite/lowlevel_init.S
@@ -0,0 +1,170 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
+SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)
+SDRAM_ESDCFG_T2_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(3)
+SDRAM_PRECHARGE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_AUTOREF_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_LOADMODE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
+				 ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_NORMAL_CMD_W:	.word	SDRAM_ESDCTL_REGISTER_VAL
+
+.macro init_aipi
+	/*
+	 * setup AIPI1 and AIPI2
+	 */
+	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
+	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
+	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
+	write32 AIPI2_PSR1, AIPI2_PSR1_VAL
+
+.endm /* init_aipi */
+
+.macro init_clock
+	ldr r0, =CSCR
+	/* disable MPLL/SPLL first */
+	ldr r1, [r0]
+	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+	str r1, [r0]
+
+	write32 MPCTL0, MPCTL0_VAL
+	write32 SPCTL0, SPCTL0_VAL
+
+	write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
+
+	/*
+	 * add some delay here
+	 */
+	wait_timer 0x1000
+
+	/* peripheral clock divider */
+	write32 PCDR0, PCDR0_VAL
+	write32 PCDR1, PCDR1_VAL
+
+	/* Configure PCCR0 and PCCR1 */
+	write32 PCCR0, PCCR0_VAL
+	write32 PCCR1, PCCR1_VAL
+
+.endm /* init_clock */
+
+.macro sdram_init
+	ldr r0, SOC_ESDCTL_BASE_W
+	mov r2, #PHYS_SDRAM_1
+
+	/* Do initial reset */
+	mov r1, #ESDMISC_MDDR_DL_RST
+	str r1, [r0, #ESDMISC_ROF]
+
+	/* Hold for more than 200ns */
+	wait_timer 0x10000
+
+	/* Activate LPDDR iface */
+	mov r1, #ESDMISC_MDDREN
+	str r1, [r0, #ESDMISC_ROF]
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG0_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+	ldrb r1, [r3]
+
+	ldr r1, SDRAM_NORMAL_CMD_W
+	str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+	/* 2nd sdram */
+	mov r2, #PHYS_SDRAM_2
+
+	/* Check The chip version TO1 or TO2 */
+	ldr r1, SOC_SI_ID_REG_W
+	ldr r1, [r1]
+	ands r1, r1, #0xF0000000
+	/* add Latency on CAS only for TO2 */
+	ldreq r1, SDRAM_ESDCFG_T2_W
+	ldrne r1, SDRAM_ESDCFG_T1_W
+	str r1, [r0, #ESDCFG1_ROF]
+
+	/* Run initialization sequence */
+	ldr r1, SDRAM_PRECHARGE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_AUTOREF_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+	ldr r1, [r2, #SDRAM_ALL_VAL]
+
+	ldr r1, SDRAM_LOADMODE_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+	ldrb r1, [r3]
+
+	ldr r1, SDRAM_NORMAL_CMD_W
+	str r1, [r0, #ESDCTL1_ROF]
+#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
+
+.endm /* sdram_init */
+
+.globl	lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+	init_aipi
+
+	init_clock
+
+	sdram_init
+
+	mov	pc,r10