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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-08-14 08:43:07 +0000
committerTom Rini <trini@ti.com>2012-10-15 11:54:14 -0700
commit9e0081d573442e7234355f0a043218d15df03933 (patch)
treebc508d9fa9b248d70cac2ed736d834d22f5e0e3b /board/imx31_phycore
parentb809b3ac13e1016b2be937bd4511973f90982ad2 (diff)
downloadu-boot-linaro-stable-9e0081d573442e7234355f0a043218d15df03933.tar.gz
mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/imx31_phycore')
-rw-r--r--board/imx31_phycore/lowlevel_init.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
index c47137d09..4dd78b660 100644
--- a/board/imx31_phycore/lowlevel_init.S
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)