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authorWolfgang Denk <wd@pollux.denx.de>2006-04-16 10:51:58 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-04-16 10:51:58 +0200
commitcf48eb9abd76e5a056937a4e49be094826026abc (patch)
tree1e05002f42f0f174f74d712b34c87ed4f99b003f /board/icecube
parent807522fc9ae49e022c9f3556506b4f4c961b17aa (diff)
downloadu-boot-linaro-stable-cf48eb9abd76e5a056937a4e49be094826026abc.tar.gz
Some code cleanup
Diffstat (limited to 'board/icecube')
-rw-r--r--board/icecube/icecube.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 4197a7c52..4f056b2fa 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -187,17 +187,17 @@ long int initdram (int board_type)
#endif /* CFG_RAMBOOT */
/*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
* parameters."
- */
+ */
svr = get_svr();
pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
+ if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;