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authorRafal Jaworowski <raj@pollux.denx.de>2006-03-29 13:17:09 +0200
committerRafal Jaworowski <raj@pollux.denx.de>2006-03-29 13:17:09 +0200
commitb66a9383421805c705654ce9456ec28c202819fb (patch)
tree4fb429d1b2402185225d8aed5fa551afff9b507a /board/icecube
parent7b4fd36b0322ec98836a8459d9be80e2777fdc05 (diff)
downloadu-boot-linaro-stable-b66a9383421805c705654ce9456ec28c202819fb.tar.gz
Set SDelay register in the DDR controller for the MPC5200B chip.
Diffstat (limited to 'board/icecube')
-rw-r--r--board/icecube/icecube.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 44831c625..4197a7c52 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
#if defined(CONFIG_LITE5200B)
#include "mt46v32m16.h"
@@ -89,6 +90,8 @@ long int initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
+
#ifndef CFG_RAMBOOT
ulong test1, test2;
@@ -183,6 +186,24 @@ long int initdram (int board_type)
#endif /* CFG_RAMBOOT */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
return dramsize + dramsize2;
}