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authorchenhui zhao <chenhui.zhao@freescale.com>2011-10-13 13:40:59 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-10-13 23:38:10 -0500
commitfff80975ae97d90418ee8989aff5a28ebaf95c5b (patch)
treef8398cd84e756c71726beb932d58622b87130ff8 /board/freescale/mpc8548cds/tlb.c
parent34fdbdf8d9819a3348b1340a5fba8ae00e768fd2 (diff)
downloadu-boot-linaro-stable-fff80975ae97d90418ee8989aff5a28ebaf95c5b.tar.gz
powerpc/mpc8548cds: Code cleanup and refactoring
- Rework tlb and law tables. - PCI2 is not available on MPC8548CDS, so remove it. - Move the memory map to the board config file. - Rewrite the board info according to the manual. - Remove unnecessary macros and redefine some macros to align with other boards. - Fix some typos. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8548cds/tlb.c')
-rw-r--r--board/freescale/mpc8548cds/tlb.c64
1 files changed, 32 insertions, 32 deletions
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index b2c1b31af..eb29e0716 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -41,63 +41,63 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */
/*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
+ * Entry 0:
+ * FLASH(cover boot page) 16M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ * Entry 1:
+ * CCSRBAR 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
+ 0, 1, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 2: 256M Non-cacheable, guarded
+ * Entry 2:
+ * LBC SDRAM 64M Cacheable, non-guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+ CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 3: 256M Non-cacheable, guarded
+ * Entry 3:
+ * CADMUS registers 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
+ 0, 3, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 1M PCI1 IO
- * 0xe210_0000 1M PCI2 IO
- * 0xe300_0000 1M PCIe IO
+ * Entry 4:
+ * PCI and PCIe MEM 1G Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
+ * Entry 5:
+ * PCI1 IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ * Entry 6:
+ * PCIe IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);