diff options
| author | wdenk <wdenk> | 2003-09-02 22:48:03 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-09-02 22:48:03 +0000 |
| commit | 12f34241cb9679c27a1ab3561766562f5a515eff (patch) | |
| tree | e6408a1701c7dabf3e2ceb1326ce2f5cc8657c96 /board/evb64260/mpsc.c | |
| parent | 326428cc8bbdddb30920a96b672abd0d59833ce4 (diff) | |
* Add support for PPChameleon Eval Board
* Add support for P3G4 board
* Fix problem with MGT5100 FEC driver: add "early" MAC address
initialization
Diffstat (limited to 'board/evb64260/mpsc.c')
| -rw-r--r-- | board/evb64260/mpsc.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index 718fe0566..ee623ca56 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -273,7 +273,7 @@ mpsc_init(int baud) /* BRG CONFIG */ galbrg_set_baudrate(CHANNEL, baud); -#ifdef CONFIG_ZUMA_V2 +#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ #else galbrg_set_clksrc(CHANNEL,0); @@ -387,7 +387,7 @@ galbrg_set_baudrate(int channel, int rate) galbrg_disable(channel); -#ifdef CONFIG_ZUMA_V2 +#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) /* from tclk */ clock = (CFG_BUS_HZ/(16*rate)) - 1; #else @@ -803,6 +803,7 @@ static int galmpsc_shutdown(int mpsc) { DECLARE_GLOBAL_DATA_PTR; +#if 0 unsigned int temp; /* cause RX abort (clears RX) */ @@ -810,9 +811,11 @@ galmpsc_shutdown(int mpsc) temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; temp &= ~MPSC_ENTER_HUNT; GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); +#endif - GT_REG_WRITE(GALSDMA_0_COM_REG, 0); - GT_REG_WRITE(GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); + GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, + SDMA_TX_ABORT | SDMA_RX_ABORT); /* shut down the MPSC */ GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); @@ -823,14 +826,15 @@ galmpsc_shutdown(int mpsc) /* shut down the sdma engines. */ /* reset config to default */ - GT_REG_WRITE(GALSDMA_0_CONF_REG, 0x000000fc); + GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF, + 0x000000fc); udelay(100); /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR, 0); + GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); udelay(100); |