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authorStefan Roese <sr@denx.de>2009-09-09 16:25:29 +0200
committerStefan Roese <sr@denx.de>2009-09-11 10:35:58 +0200
commitd1c3b27525b664e8c4db6bb173eed51bfc8220de (patch)
treec00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/amcc/ebony
parente7963772eb78a6aa1fa65063d64eab3a8626daac (diff)
downloadu-boot-linaro-stable-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.gz
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/ebony')
-rw-r--r--board/amcc/ebony/ebony.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index ad09e6207..2439b03a9 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -41,30 +41,30 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
- mtdcr(ebccfga, xbcfg);
- reg = mfdcr(ebccfgd);
- mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ reg = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
- mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
- mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
- mtebc(pb7ap, 0x01015280); /* FPGA registers */
- mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
+ mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
+ mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
+ mtebc(PB7AP, 0x01015280); /* FPGA registers */
+ mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
- mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
- mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
- mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
+ mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
+ mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
+ mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
- mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
- mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
+ mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
+ mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
- mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
- mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
+ mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
+ mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
@@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose)
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
- strap = mfdcr(cpc0_strp1);
+ strap = mfdcr(CPC0_STRP1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;