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authorTom Rini <trini@ti.com>2012-07-30 14:49:50 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-05 22:02:39 +0200
commitd0adb945e64ee7f31c34dc712cf5658e231b6688 (patch)
treec11770fe1a8519e444275048b0b12b8e34707996 /arch
parent08d0203712e182ac48a8befd525e3038869ac879 (diff)
downloadu-boot-linaro-stable-d0adb945e64ee7f31c34dc712cf5658e231b6688.tar.gz
am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c2
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c41
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h17
3 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index bceed8150..cffd4abcf 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -46,6 +46,8 @@ void config_sdram(const struct emif_regs *regs)
{
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+ if (regs->zq_config)
+ writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
}
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 171d764e6..b2d7c0d95 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -87,6 +87,38 @@ static const struct emif_regs ddr2_emif_reg_data = {
.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
};
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = DDR3_RD_DQS,
+ .datawdsratio0 = DDR3_WR_DQS,
+ .datafwsratio0 = DDR3_PHY_FIFO_WE,
+ .datawrsratio0 = DDR3_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = DDR3_RATIO,
+ .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd0iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd1csratio = DDR3_RATIO,
+ .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd1iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd2csratio = DDR3_RATIO,
+ .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd2iclkout = DDR3_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = DDR3_EMIF_SDCFG,
+ .ref_ctrl = DDR3_EMIF_SDREF,
+ .sdram_tim1 = DDR3_EMIF_TIM1,
+ .sdram_tim2 = DDR3_EMIF_TIM2,
+ .sdram_tim3 = DDR3_EMIF_TIM3,
+ .zq_config = DDR3_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
+};
+
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -115,6 +147,15 @@ void config_ddr(short ddr_type)
ddr_data = &ddr2_data;
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
+ } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
+ ddr_pll = 303;
+ cmd_ctrl_data = &ddr3_cmd_ctrl_data;
+ ddr_data = &ddr3_data;
+ ioctrl_val = DDR3_IOCTRL_VALUE;
+ emif_regs = &ddr3_emif_reg_data;
+ } else {
+ puts("Unknown memory type");
+ hang();
}
enable_emif_clocks();
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 052686369..6b22c45f7 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -47,6 +47,23 @@
#define DDR2_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1 0x0888A39B
+#define DDR3_EMIF_TIM2 0x26337FDA
+#define DDR3_EMIF_TIM3 0x501F830F
+#define DDR3_EMIF_SDCFG 0x61C04AB2
+#define DDR3_EMIF_SDREF 0x0000093B
+#define DDR3_ZQ_CFG 0x50074BE4
+#define DDR3_DLL_LOCK_DIFF 0x1
+#define DDR3_RATIO 0x40
+#define DDR3_INVERT_CLKOUT 0x1
+#define DDR3_RD_DQS 0x3B
+#define DDR3_WR_DQS 0x85
+#define DDR3_PHY_WR_DATA 0xC1
+#define DDR3_PHY_FIFO_WE 0x100
+#define DDR3_IOCTRL_VALUE 0x18B
+
/**
* Configure SDRAM
*/