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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-10-26 07:00:28 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-10-26 07:00:28 +0200
commitc68436fa427a69ea308d74c410067507d6c7103b (patch)
tree4f05a23bb3eabfe1eaf1f92bf6f57a6e403ac9a4 /arch
parent186fc4db263fc6332d6712be99a9a387087d29c7 (diff)
parentc7d35bef255dedb3ec3856982f042dde514676b0 (diff)
downloadu-boot-linaro-stable-c68436fa427a69ea308d74c410067507d6c7103b.tar.gz
Merge remote-tracking branch 'u-boot-ti/master'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/Makefile1
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c239
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c6
-rw-r--r--arch/arm/cpu/armv7/am33xx/config.mk1
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c114
-rw-r--r--arch/arm/cpu/armv7/am33xx/mux.c33
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h15
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h69
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware.h4
-rw-r--r--arch/arm/include/asm/arch-am33xx/mux.h261
-rw-r--r--arch/arm/include/asm/arch-am33xx/spl.h1
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h27
-rw-r--r--arch/arm/include/asm/arch-omap3/dss.h1
13 files changed, 372 insertions, 400 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 776891260..74875b325 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -21,6 +21,7 @@ COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
+COBJS += mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184fb..e4c123cd2 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -36,9 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-
static const struct gpio_bank gpio_bank_am33xx[4] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
-/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
- return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
- return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally "
- "wrong on the I2C bus.\n");
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
- puts("Could not read the EEPROM; something fundamentally"
- " wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header.magic != 0xEE3355AA) {
- /*
- * read the eeprom using i2c again,
- * but use only a 1 byte address
- */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
- (uchar *)&header, sizeof(header))) {
- puts("Could not read the EEPROM; something "
- "fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header.magic != 0xEE3355AA) {
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header.magic);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-#endif
-
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
- /* The following boards are known to use DDR3. */
- if (board_is_evm_sk())
- return EMIF_REG_SDRAM_TYPE_DDR3;
-
- return EMIF_REG_SDRAM_TYPE_DDR2;
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
-{
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-
-#ifdef CONFIG_SPL_BUILD
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
-
- /* UART softreset */
- u32 regVal;
-
- enable_uart0_pin_mux();
-
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
-
- gd = &gdata;
-
- preloader_console_init();
-
- /* Initalize the board header */
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
- enable_board_pin_mux(&header);
- if (board_is_evm_sk()) {
- /*
- * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
- }
-
- config_ddr(board_memory_type());
-#endif
-}
-
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+int cpu_mmc_init(bd_t *bis)
{
int ret;
-
+
ret = omap_mmc_init(0, 0, 0);
if (ret)
return ret;
@@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
-
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_id = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_id = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = AM335X_CPSW_MDIO_BASE,
- .cpsw_base = AM335X_CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
- debug("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- else
- return -1;
- }
-
- if (board_is_bone()) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_MII;
- } else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_RGMII;
- }
-
- return cpsw_register(&cpsw_data);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506a3..f87085941 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -44,6 +44,7 @@
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
static void enable_interface_clocks(void)
{
@@ -153,6 +154,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
+
+ /* RTC */
+ writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+ while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5750bbdcb..babf0eb5c 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -13,6 +13,7 @@
#
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
else
ALL-y += $(obj)u-boot.img
endif
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index b2d7c0d95..01e3a5204 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,78 +47,6 @@ void dram_init_banksize(void)
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
- .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
- .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
- .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
- .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
- .datauserank0delay = DDR2_PHY_RANK0_DELAY,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = DDR2_RATIO,
- .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd0iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd1csratio = DDR2_RATIO,
- .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd1iclkout = DDR2_INVERT_CLKOUT,
-
- .cmd2csratio = DDR2_RATIO,
- .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
- .cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
- .sdram_config = DDR2_EMIF_SDCFG,
- .ref_ctrl = DDR2_EMIF_SDREF,
- .sdram_tim1 = DDR2_EMIF_TIM1,
- .sdram_tim2 = DDR2_EMIF_TIM2,
- .sdram_tim3 = DDR2_EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = DDR3_RD_DQS,
- .datawdsratio0 = DDR3_WR_DQS,
- .datafwsratio0 = DDR3_PHY_FIFO_WE,
- .datawrsratio0 = DDR3_PHY_WR_DATA,
- .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = DDR3_RATIO,
- .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd0iclkout = DDR3_INVERT_CLKOUT,
-
- .cmd1csratio = DDR3_RATIO,
- .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd1iclkout = DDR3_INVERT_CLKOUT,
-
- .cmd2csratio = DDR3_RATIO,
- .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
- .cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = DDR3_EMIF_SDCFG,
- .ref_ctrl = DDR3_EMIF_SDREF,
- .sdram_tim1 = DDR3_EMIF_TIM1,
- .sdram_tim2 = DDR3_EMIF_TIM2,
- .sdram_tim3 = DDR3_EMIF_TIM3,
- .zq_config = DDR3_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -134,46 +62,26 @@ static void config_vtp(void)
;
}
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs)
{
- int ddr_pll, ioctrl_val;
- const struct emif_regs *emif_regs;
- const struct ddr_data *ddr_data;
- const struct cmd_control *cmd_ctrl_data;
-
- if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
- ddr_pll = 266;
- cmd_ctrl_data = &ddr2_cmd_ctrl_data;
- ddr_data = &ddr2_data;
- ioctrl_val = DDR2_IOCTRL_VALUE;
- emif_regs = &ddr2_emif_reg_data;
- } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
- ddr_pll = 303;
- cmd_ctrl_data = &ddr3_cmd_ctrl_data;
- ddr_data = &ddr3_data;
- ioctrl_val = DDR3_IOCTRL_VALUE;
- emif_regs = &ddr3_emif_reg_data;
- } else {
- puts("Unknown memory type");
- hang();
- }
-
enable_emif_clocks();
- ddr_pll_config(ddr_pll);
+ ddr_pll_config(pll);
config_vtp();
- config_cmd_ctrl(cmd_ctrl_data);
+ config_cmd_ctrl(ctrl);
- config_ddr_data(0, ddr_data);
- config_ddr_data(1, ddr_data);
+ config_ddr_data(0, data);
+ config_ddr_data(1, data);
- config_io_ctrl(ioctrl_val);
+ config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
- config_ddr_phy(emif_regs);
- set_sdram_timings(emif_regs);
- config_sdram(emif_regs);
+ config_ddr_phy(regs);
+ set_sdram_timings(regs);
+ config_sdram(regs);
}
#endif
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644
index 000000000..2ded47228
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+ int i;
+
+ if (!mod_pin_mux)
+ return;
+
+ for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+ MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef76a..819fd2f02 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -169,6 +169,12 @@ struct cm_dpll {
unsigned int clktimer2clk; /* offset 0x08 */
};
+/* Control Module RTC registers */
+struct cm_rtc {
+ unsigned int rtcclkctrl; /* offset 0x0 */
+ unsigned int clkstctrl; /* offset 0x4 */
+};
+
/* Watchdog timer registers */
struct wd_timer {
unsigned int resv1[4];
@@ -218,6 +224,15 @@ struct gptimer {
unsigned int tcar2; /* offset 0x58 */
};
+/* RTC Registers */
+struct rtc_regs {
+ unsigned int res[21];
+ unsigned int osc; /* offset 0x54 */
+ unsigned int res2[5];
+ unsigned int kick0r; /* offset 0x6c */
+ unsigned int kick1r; /* offset 0x70 */
+};
+
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6b22c45f7..8e69fb67b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,40 +29,41 @@
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
-#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1 0x0666B3C9
-#define DDR2_EMIF_TIM2 0x243631CA
-#define DDR2_EMIF_TIM3 0x0000033F
-#define DDR2_EMIF_SDCFG 0x41805332
-#define DDR2_EMIF_SDREF 0x0000081a
-#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RATIO 0x80
-#define DDR2_INVERT_CLKOUT 0x00
-#define DDR2_RD_DQS 0x12
-#define DDR2_WR_DQS 0x00
-#define DDR2_PHY_WRLVL 0x00
-#define DDR2_PHY_GATELVL 0x00
-#define DDR2_PHY_WR_DATA 0x40
-#define DDR2_PHY_FIFO_WE 0x80
-#define DDR2_PHY_RANK0_DELAY 0x1
-#define DDR2_IOCTRL_VALUE 0x18B
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
+#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
+#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
+#define MT47H128M16RT25E_RATIO 0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
+#define MT47H128M16RT25E_RD_DQS 0x12
+#define MT47H128M16RT25E_WR_DQS 0x00
+#define MT47H128M16RT25E_PHY_WRLVL 0x00
+#define MT47H128M16RT25E_PHY_GATELVL 0x00
+#define MT47H128M16RT25E_PHY_WR_DATA 0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
+#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
+#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY 0x06
-#define DDR3_EMIF_TIM1 0x0888A39B
-#define DDR3_EMIF_TIM2 0x26337FDA
-#define DDR3_EMIF_TIM3 0x501F830F
-#define DDR3_EMIF_SDCFG 0x61C04AB2
-#define DDR3_EMIF_SDREF 0x0000093B
-#define DDR3_ZQ_CFG 0x50074BE4
-#define DDR3_DLL_LOCK_DIFF 0x1
-#define DDR3_RATIO 0x40
-#define DDR3_INVERT_CLKOUT 0x1
-#define DDR3_RD_DQS 0x3B
-#define DDR3_WR_DQS 0x85
-#define DDR3_PHY_WR_DATA 0xC1
-#define DDR3_PHY_FIFO_WE 0x100
-#define DDR3_IOCTRL_VALUE 0x18B
+#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
+#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3 0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF 0x0000093B
+#define MT41J128MJT125_ZQ_CFG 0x50074BE4
+#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
+#define MT41J128MJT125_RATIO 0x40
+#define MT41J128MJT125_INVERT_CLKOUT 0x1
+#define MT41J128MJT125_RD_DQS 0x3B
+#define MT41J128MJT125_WR_DQS 0x85
+#define MT41J128MJT125_PHY_WR_DATA 0xC1
+#define MT41J128MJT125_PHY_FIFO_WE 0x100
+#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/**
* Configure SDRAM
@@ -189,6 +190,8 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+ const struct ddr_data *data, const struct cmd_control *ctrl,
+ const struct emif_regs *regs);
#endif /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2de..5bd4bc872 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,6 +61,7 @@
#define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
+#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
@@ -83,4 +84,7 @@
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
+/* RTC base address */
+#define AM335X_RTC_BASE 0x44E3E000
+
#endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 000000000..aed6b00cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,261 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+ __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) val /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct module_pin_mux {
+ short reg_offset;
+ unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 63ed10b25..644ff353f 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -27,6 +27,7 @@
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
+#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea650f..9cf35e025 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -19,24 +19,6 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-struct am335x_baseboard_id {
- unsigned int magic;
- char name[HDR_NAME_LEN];
- char version[4];
- char serial[12];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
#define BOARD_REV_ID 0x0
u32 get_cpu_rev(void);
@@ -51,13 +33,4 @@ u32 get_device_type(void);
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index 54add4b45..ffaffbb3b 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -190,6 +190,7 @@ struct panel_config {
#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,