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authorMarek Vasut <marex@denx.de>2012-10-03 08:54:09 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-10-26 22:37:12 +0200
commitafad40299eea12dfd032b44d04c2d4151d7e9862 (patch)
tree417be44c334316e52d416bdbaf68d5a41edd375c /arch
parent6f62f4207112013852be87dc2b9c7c570eba11c9 (diff)
downloadu-boot-linaro-stable-afad40299eea12dfd032b44d04c2d4151d7e9862.tar.gz
arm: Remove support for s3c4510
This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/arm720t/cpu.c2
-rw-r--r--arch/arm/cpu/arm720t/interrupts.c106
-rw-r--r--arch/arm/cpu/arm720t/s3c4510b/Makefile45
-rw-r--r--arch/arm/cpu/arm720t/s3c4510b/cache.c86
-rw-r--r--arch/arm/cpu/arm720t/start.S19
-rw-r--r--arch/arm/include/asm/arch-s3c4510b/hardware.h272
6 files changed, 2 insertions, 528 deletions
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
index e25f6f2ea..864720fcd 100644
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
@@ -46,7 +46,7 @@ int cleanup_before_linux (void)
* and we set the CPU-speed to 73 MHz - see start.S for details
*/
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+#if defined(CONFIG_NETARM)
disable_interrupts ();
/* Nothing more needed */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index 5b21cc3ce..e3b59fef0 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -45,28 +45,10 @@
#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
#endif
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif /* CONFIG_S3C4510B */
-
#ifdef CONFIG_USE_IRQ
void do_irq (struct pt_regs *pt_regs)
{
-#if defined(CONFIG_S3C4510B)
- unsigned int pending;
-
- while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
- IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
- /* clear pending interrupt */
- PUT_REG( REG_INTPEND, (1<<(pending>>2)));
- }
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No do_irq() for IntegratorAP/CM720T as yet */
#else
#error do_irq() not defined for this CPU type
@@ -74,23 +56,6 @@ void do_irq (struct pt_regs *pt_regs)
}
#endif
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
- printf ("default_isr(): called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
- unsigned int *pTime = (unsigned int *)data;
-
- (*pTime)++;
- if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
- /* toggle LED 0 */
- PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
- }
-
-}
-#endif
-
#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* Use IntegratorAP routines in board/integratorap.c */
#else
@@ -98,32 +63,6 @@ static void timer_isr( void *data) {
static ulong timestamp;
static ulong lastdec;
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
- int i;
-
- /* install default interrupt handlers */
- for ( i = 0; i < N_IRQS; i++) {
- IRQ_HANDLER[i].m_data = (void *)i;
- IRQ_HANDLER[i].m_func = default_isr;
- }
-
- /* configure interrupts for IRQ mode */
- PUT_REG( REG_INTMODE, 0x0);
- /* clear any pending interrupts */
- PUT_REG( REG_INTPEND, 0x1FFFFF);
-
- lastdec = 0;
-
- /* install interrupt handler for timer */
- IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
- IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
- return 0;
-}
-#endif
-
int timer_init (void)
{
#if defined(CONFIG_NETARM)
@@ -137,29 +76,6 @@ int timer_init (void)
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
- /* configure free running timer 0 */
- PUT_REG( REG_TMOD, 0x0);
- /* Stop timer 0 */
- CLR_REG( REG_TMOD, TM0_RUN);
-
- /* Configure for interval mode */
- CLR_REG( REG_TMOD, TM1_TOGGLE);
-
- /*
- * Load Timer data register with count down value.
- * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
- */
- PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
- /*
- * Enable global interrupt
- * Enable timer0 interrupt
- */
- CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
- /* Start timer */
- SET_REG( REG_TMOD, TM0_RUN);
#elif defined(CONFIG_TEGRA)
/* No timer routines for tegra as yet */
lastdec = 0;
@@ -237,26 +153,6 @@ void udelay_masked (unsigned long usec)
} while (diff >= 0);
}
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
- return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
- u32 ticks;
-
- ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
- ticks += get_timer (0);
-
- while (get_timer (0) < ticks)
- /*NOP*/;
-
-}
-
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No timer routines for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_TEGRA)
diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile
deleted file mode 100644
index 5c6df08b1..000000000
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-COBJS-y += cache.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644
index 104d287b2..000000000
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
- s32 i;
-
- /* disable all cache bits */
- CLR_REG( REG_SYSCFG, 0x3F);
-
- /* 8KB cache, write enable */
- SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
- /* clear TAG RAM bits */
- for ( i = 0; i < 256; i++)
- PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
- /* clear SET0 RAM */
- for(i=0; i < 1024; i++)
- PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
- /* clear SET1 RAM */
- for(i=0; i < 1024; i++)
- PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
- /* enable cache */
- SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
- /* disable all cache bits */
- CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
- return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
- /* we don't have seperate instruction/data caches */
- icache_enable();
-}
-
-void dcache_disable (void)
-{
- /* we don't have seperate instruction/data caches */
- icache_disable();
-}
-
-int dcache_status (void)
-{
- /* we don't have seperate instruction/data caches */
- return icache_status();
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0daf84811..3a90e0d77 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -335,22 +335,6 @@ cpu_init_crit:
ldr r0, =NETARM_GEN_MODULE_BASE
str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-#elif defined(CONFIG_S3C4510B)
-
- /*
- * Mask off all IRQ sources
- */
- ldr r1, =REG_INTMASK
- ldr r0, =0x3FFFFF
- str r0, [r1]
-
- /*
- * Disable Cache
- */
- ldr r0, =REG_SYSCFG
- ldr r1, =0x83ffffa0 /* cache-disabled */
- str r1, [r0]
-
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific initialisation for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_TEGRA)
@@ -569,9 +553,6 @@ reset_cpu:
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
mov pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific reset actions for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_TEGRA)
diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h
deleted file mode 100644
index 6b8c8edd7..000000000
--- a/arch/arm/include/asm/arch-s3c4510b/hardware.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __HW_S3C4510_H
-#define __HW_S3C4510_H
-
-/*
- * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description: Samsung S3C4510B register layout
- */
-
-/*------------------------------------------------------------------------
- * ASIC Address Definition
- *----------------------------------------------------------------------*/
-
-/* L1 8KB on chip SRAM base address */
-#define SRAM_BASE (0x03fe0000)
-
-/* Special Register Start Address After System Reset */
-#define REG_BASE (0x03ff0000)
-#define SPSTR (REG_BASE)
-
-/* *********************** */
-/* System Manager Register */
-/* *********************** */
-#define REG_SYSCFG (REG_BASE+0x0000)
-
-#define REG_CLKCON (REG_BASE+0x3000)
-#define REG_EXTACON0 (REG_BASE+0x3008)
-#define REG_EXTACON1 (REG_BASE+0x300c)
-#define REG_EXTDBWTH (REG_BASE+0x3010)
-#define REG_ROMCON0 (REG_BASE+0x3014)
-#define REG_ROMCON1 (REG_BASE+0x3018)
-#define REG_ROMCON2 (REG_BASE+0x301c)
-#define REG_ROMCON3 (REG_BASE+0x3020)
-#define REG_ROMCON4 (REG_BASE+0x3024)
-#define REG_ROMCON5 (REG_BASE+0x3028)
-#define REG_DRAMCON0 (REG_BASE+0x302c)
-#define REG_DRAMCON1 (REG_BASE+0x3030)
-#define REG_DRAMCON2 (REG_BASE+0x3034)
-#define REG_DRAMCON3 (REG_BASE+0x3038)
-#define REG_REFEXTCON (REG_BASE+0x303c)
-
-/* *********************** */
-/* Ethernet BDMA Register */
-/* *********************** */
-#define REG_BDMATXCON (REG_BASE+0x9000)
-#define REG_BDMARXCON (REG_BASE+0x9004)
-#define REG_BDMATXPTR (REG_BASE+0x9008)
-#define REG_BDMARXPTR (REG_BASE+0x900c)
-#define REG_BDMARXLSZ (REG_BASE+0x9010)
-#define REG_BDMASTAT (REG_BASE+0x9014)
-
-/* Content Address Memory */
-#define REG_CAM_BASE (REG_BASE+0x9100)
-
-#define REG_BDMATXBUF (REG_BASE+0x9200)
-#define REG_BDMARXBUF (REG_BASE+0x9800)
-
-/* *********************** */
-/* Ethernet MAC Register */
-/* *********************** */
-#define REG_MACCON (REG_BASE+0xa000)
-#define REG_CAMCON (REG_BASE+0xa004)
-#define REG_MACTXCON (REG_BASE+0xa008)
-#define REG_MACTXSTAT (REG_BASE+0xa00c)
-#define REG_MACRXCON (REG_BASE+0xa010)
-#define REG_MACRXSTAT (REG_BASE+0xa014)
-#define REG_STADATA (REG_BASE+0xa018)
-#define REG_STACON (REG_BASE+0xa01c)
-#define REG_CAMEN (REG_BASE+0xa028)
-#define REG_EMISSCNT (REG_BASE+0xa03c)
-#define REG_EPZCNT (REG_BASE+0xa040)
-#define REG_ERMPZCNT (REG_BASE+0xa044)
-#define REG_ETXSTAT (REG_BASE+0x9040)
-#define REG_MACRXDESTR (REG_BASE+0xa064)
-#define REG_MACRXSTATEM (REG_BASE+0xa090)
-#define REG_MACRXFIFO (REG_BASE+0xa200)
-
-/********************/
-/* I2C Bus Register */
-/********************/
-#define REG_I2C_CON (REG_BASE+0xf000)
-#define REG_I2C_BUF (REG_BASE+0xf004)
-#define REG_I2C_PS (REG_BASE+0xf008)
-#define REG_I2C_COUNT (REG_BASE+0xf00c)
-
-/********************/
-/* GDMA 0 */
-/********************/
-#define REG_GDMACON0 (REG_BASE+0xb000)
-#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
-#define REG_GDMASRC0 (REG_BASE+0xb004)
-#define REG_GDMADST0 (REG_BASE+0xb008)
-#define REG_GDMACNT0 (REG_BASE+0xb00c)
-
-/********************/
-/* GDMA 1 */
-/********************/
-#define REG_GDMACON1 (REG_BASE+0xc000)
-#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
-#define REG_GDMASRC1 (REG_BASE+0xc004)
-#define REG_GDMADST1 (REG_BASE+0xc008)
-#define REG_GDMACNT1 (REG_BASE+0xc00c)
-
-/********************/
-/* UART 0 */
-/********************/
-#define UART0_BASE (REG_BASE+0xd000)
-#define REG_UART0_LCON (REG_BASE+0xd000)
-#define REG_UART0_CTRL (REG_BASE+0xd004)
-#define REG_UART0_STAT (REG_BASE+0xd008)
-#define REG_UART0_TXB (REG_BASE+0xd00c)
-#define REG_UART0_RXB (REG_BASE+0xd010)
-#define REG_UART0_BAUD_DIV (REG_BASE+0xd014)
-#define REG_UART0_BAUD_CNT (REG_BASE+0xd018)
-#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C)
-
-/********************/
-/* UART 1 */
-/********************/
-#define UART1_BASE (REG_BASE+0xe000)
-#define REG_UART1_LCON (REG_BASE+0xe000)
-#define REG_UART1_CTRL (REG_BASE+0xe004)
-#define REG_UART1_STAT (REG_BASE+0xe008)
-#define REG_UART1_TXB (REG_BASE+0xe00c)
-#define REG_UART1_RXB (REG_BASE+0xe010)
-#define REG_UART1_BAUD_DIV (REG_BASE+0xe014)
-#define REG_UART1_BAUD_CNT (REG_BASE+0xe018)
-#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C)
-
-/********************/
-/* Timer Register */
-/********************/
-#define REG_TMOD (REG_BASE+0x6000)
-#define REG_TDATA0 (REG_BASE+0x6004)
-#define REG_TDATA1 (REG_BASE+0x6008)
-#define REG_TCNT0 (REG_BASE+0x600c)
-#define REG_TCNT1 (REG_BASE+0x6010)
-
-/**********************/
-/* I/O Port Interface */
-/**********************/
-#define REG_IOPMODE (REG_BASE+0x5000)
-#define REG_IOPCON (REG_BASE+0x5004)
-#define REG_IOPDATA (REG_BASE+0x5008)
-
-/*********************************/
-/* Interrupt Controller Register */
-/*********************************/
-#define REG_INTMODE (REG_BASE+0x4000)
-#define REG_INTPEND (REG_BASE+0x4004)
-#define REG_INTMASK (REG_BASE+0x4008)
-
-#define REG_INTPRI0 (REG_BASE+0x400c)
-#define REG_INTPRI1 (REG_BASE+0x4010)
-#define REG_INTPRI2 (REG_BASE+0x4014)
-#define REG_INTPRI3 (REG_BASE+0x4018)
-#define REG_INTPRI4 (REG_BASE+0x401c)
-#define REG_INTPRI5 (REG_BASE+0x4020)
-#define REG_INTOFFSET (REG_BASE+0x4024)
-#define REG_INTPNDPRI (REG_BASE+0x4028)
-#define REG_INTPNDTST (REG_BASE+0x402C)
-
-/*********************************/
-/* CACHE CONTROL MASKS */
-/*********************************/
-#define CACHE_STALL (0x00000001)
-#define CACHE_ENABLE (0x00000002)
-#define CACHE_WRITE_BUFF (0x00000004)
-#define CACHE_MODE (0x00000030)
-#define CACHE_MODE_00 (0x00000000)
-#define CACHE_MODE_01 (0x00000010)
-#define CACHE_MODE_10 (0x00000020)
-
-/*********************************/
-/* CACHE RAM BASE ADDRESSES */
-/*********************************/
-#define CACHE_SET0_RAM (0x10000000)
-#define CACHE_SET1_RAM (0x10800000)
-#define CACHE_TAG_RAM (0x11000000)
-
-/*********************************/
-/* CACHE_DISABLE MASK */
-/*********************************/
-#define CACHE_DISABLE_MASK (0x04000000)
-
-#define GET_REG(reg) (*((volatile u32 *)(reg)))
-#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val)))
-#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask))
-#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
-#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val)))
-#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF)))
-#define GET__U8(reg) (*((volatile u8 *)(reg)))
-
-#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF))
-#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF)
-#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); }
-#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); }
-
-/***********************************/
-/* CLOCK CONSTANTS -- 50 MHz Clock */
-/***********************************/
-
-#define CLK_FREQ_MHZ (50)
-#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */
-#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */
-
-/*********************************************************/
-/* TIMER MODE REGISTER */
-/*********************************************************/
-#define TM0_RUN 0x01 /* Timer 0 enable */
-#define TM0_TOGGLE 0x02 /* 0, interval mode */
-#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
-#define TM1_RUN 0x08 /* Timer 1 enable */
-#define TM1_TOGGLE 0x10 /* 0, interval mode */
-#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
-
-
-/*********************************/
-/* INTERRUPT SOURCES */
-/*********************************/
-#define INT_EXTINT0 0
-#define INT_EXTINT1 1
-#define INT_EXTINT2 2
-#define INT_EXTINT3 3
-#define INT_UARTTX0 4
-#define INT_UARTRX0 5
-#define INT_UARTTX1 6
-#define INT_UARTRX1 7
-#define INT_GDMA0 8
-#define INT_GDMA1 9
-#define INT_TIMER0 10
-#define INT_TIMER1 11
-#define INT_HDLCTXA 12
-#define INT_HDLCRXA 13
-#define INT_HDLCTXB 14
-#define INT_HDLCRXB 15
-#define INT_BDMATX 16
-#define INT_BDMARX 17
-#define INT_MACTX 18
-#define INT_MACRX 19
-#define INT_IIC 20
-#define INT_GLOBAL 21
-#define N_IRQS (21)
-
-#ifndef __ASSEMBLER__
-struct _irq_handler {
- void *m_data;
- void (*m_func)( void *data);
-};
-
-#endif
-
-#endif /* __S3C4510_h */