Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

16 files changed, 518 insertions, 57 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e94975a1c..7b9f77362 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -44,6 +44,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
 	puts("Work-around for Erratum SERDES8 enabled\n");
 #endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
+	puts("Work-around for Erratum SERDES9 enabled\n");
+#endif
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
+	puts("Work-around for Erratum SERDES-A005 enabled\n");
+#endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
 	puts("Work-around for Erratum CPU22 enabled\n");
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f5b39c067..f863f4aad 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -234,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 /*
  * Get timebase clock frequency
  */
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
 unsigned long get_tbclk (void)
 {
-#ifdef CONFIG_FSL_CORENET
-	return (gd->bus_clk + 8) / 16;
-#else
-	return (gd->bus_clk + 4UL)/8UL;
-#endif
+	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
+
+	return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
 }
 
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6f256cf7a..b3da970d4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -436,6 +436,23 @@ int cpu_init_r(void)
 	isync();
 #endif
 
+#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
+	{
+		ccsr_usb_phy_t *usb_phy1 =
+			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+		out_be32(&usb_phy1->usb_enable_override,
+				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+	}
+#endif
+#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
+	{
+		ccsr_usb_phy_t *usb_phy2 =
+			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+		out_be32(&usb_phy2->usb_enable_override,
+				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+	}
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 642f6c54b..6e909b52d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -473,6 +473,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_portal(blob, "fsl,bman-portal", "bman-portals",
 			(u64)CONFIG_SYS_BMAN_MEM_PHYS,
 			CONFIG_SYS_BMAN_MEM_SIZE);
+	fdt_fixup_bportals(blob);
 #endif
 
 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index f58d6d617..741a0f84a 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -29,6 +29,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/fsl_law.h>
+#include <asm/errno.h>
 #include "fsl_corenet_serdes.h"
 
 static u32 serdes_prtcl_map;
@@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane)
 	return lanes[lane].idx;
 }
 
-int serdes_get_bank(int lane)
+int serdes_get_bank_by_lane(int lane)
 {
 	return lanes[lane].bank;
 }
@@ -132,6 +133,125 @@ int is_serdes_configured(enum srds_prtcl device)
 	return (1 << device) & serdes_prtcl_map;
 }
 
+static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
+{
+	int i;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(prtcl, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+/*
+ * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
+ * device. This depends on the current SERDES protocol, as defined in the RCW.
+ *
+ * Returns a negative error code if SERDES is disabled or the given device is
+ * not supported in the current SERDES protocol.
+ */
+int serdes_get_first_lane(enum srds_prtcl device)
+{
+	u32 prtcl;
+	const ccsr_gur_t *gur;
+
+	gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Is serdes enabled at all? */
+	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
+		return -ENODEV;
+
+	prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	return __serdes_get_first_lane(prtcl, device);
+}
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+/*
+ * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
+ * SERDES protocol.
+ *
+ * Returns a negative error code if the given device is not supported for the
+ * given SERDES protocol.
+ */
+static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
+{
+	int lane;
+
+	lane = __serdes_get_first_lane(prtcl, device);
+	if (unlikely(lane < 0))
+		return lane;
+
+	return serdes_get_bank_by_lane(lane);
+}
+
+static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
+					int first)
+{
+	int lane;
+
+	for (lane = first; lane < SRDS_MAX_LANES; lane++) {
+		if (serdes_get_prtcl(prtcl, lane) != device)
+			break;
+	}
+
+	return lane - first;
+}
+
+static void __serdes_reset_rx(serdes_corenet_t *regs,
+			      uint32_t prtcl,
+			      enum srds_prtcl device)
+{
+	int lane, idx, first, last;
+
+	lane = __serdes_get_first_lane(prtcl, device);
+	if (unlikely(lane < 0))
+		return;
+	first = serdes_get_lane_idx(lane);
+	last = first + __serdes_get_lane_count(prtcl, device, lane);
+
+	/*
+	 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
+	 * selected as XAUI to place the lane into reset.
+	*/
+	for (idx = first; idx < last; idx++)
+		clrbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
+
+	/* Wait at least 250 ns */
+	udelay(1);
+
+	/*
+	 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
+	 * selected as XAUI to bring the lane out of reset.
+	 */
+	for (idx = first; idx < last; idx++)
+		setbits_be32(&regs->lane[idx].gcr0, SRDS_GCR0_RRST);
+}
+
+void serdes_reset_rx(enum srds_prtcl device)
+{
+	u32 prtcl;
+	const ccsr_gur_t *gur;
+	serdes_corenet_t *regs;
+
+	if (unlikely(device == NONE))
+		return;
+
+	gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Is serdes enabled at all? */
+	if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
+		return;
+
+	regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+	__serdes_reset_rx(regs, prtcl, device);
+}
+#endif
+
 #ifndef CONFIG_SYS_DCSRBAR_PHYS
 #define CONFIG_SYS_DCSRBAR_PHYS	0x80000000 /* Must be 1GB-aligned for rev1.0 */
 #define CONFIG_SYS_DCSRBAR	0x80000000
@@ -266,6 +386,74 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
 }
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+/*
+ * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
+ * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
+ */
+static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
+{
+	enum srds_prtcl device;
+
+	switch (cfg) {
+	case 0x13:
+	case 0x16:
+		/*
+		 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
+		 * to 0.
+		 */
+		clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
+			     SRDS_PLLCR1_PLL_BWSEL);
+		break;
+	case 0x19:
+		/*
+		 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
+		 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
+		 */
+		clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1,
+			     SRDS_PLLCR1_PLL_BWSEL);
+		setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
+			     SRDS_PLLCR1_PLL_BWSEL);
+		break;
+	}
+
+	/*
+	 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
+	 * before XAUI is initialized.
+	 */
+	for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
+		if (is_serdes_configured(device)) {
+			int bank = serdes_get_bank_by_device(cfg, device);
+
+			clrbits_be32(&regs->bank[bank].pllcr1,
+				     SRDS_PLLCR1_PLL_BWSEL);
+		}
+	}
+}
+#endif
+
+/*
+ * Wait for the RSTDONE bit to get set, or a one-second timeout.
+ */
+static void wait_for_rstdone(unsigned int bank)
+{
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	unsigned long long end_tick;
+	u32 rstctl;
+
+	/* wait for reset complete or 1-second timeout */
+	end_tick = usec2ticks(1000000) + get_ticks();
+	do {
+		rstctl = in_be32(&srds_regs->bank[bank].rstctl);
+		if (rstctl & SRDS_RSTCTL_RSTDONE)
+			break;
+	} while (end_tick > get_ticks());
+
+	if (!(rstctl & SRDS_RSTCTL_RSTDONE))
+		printf("SERDES: timeout resetting bank %u\n", bank);
+}
+
 void fsl_serdes_init(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -273,7 +461,6 @@ void fsl_serdes_init(void)
 	serdes_corenet_t *srds_regs;
 	int lane, bank, idx;
 	enum srds_prtcl lane_prtcl;
-	long long end_tick;
 	int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	u32 serdes8_devdisr = 0;
@@ -282,6 +469,12 @@ void fsl_serdes_init(void)
 	const char *srds_lpd_arg;
 	size_t arglen;
 #endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+	enum srds_prtcl device;
+#endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
+	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
+#endif
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
 
@@ -307,6 +500,17 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	/*
+	 * Display a warning if banks two and three are not disabled in the RCW,
+	 * since our work-around for SERDES8 depends on these banks being
+	 * disabled at power-on.
+	 */
+#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
+	if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
+		printf("Warning: SERDES8 requires banks two and "
+		       "three to be disabled in the RCW\n");
+	}
+
+	/*
 	 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
 	 * hwconfig options into the srds_lpd_b[] array.  See README.p4080ds
 	 * for a description of these options.
@@ -325,7 +529,7 @@ void fsl_serdes_init(void)
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
 		if (serdes_lane_enabled(lane)) {
-			have_bank[serdes_get_bank(lane)] = 1;
+			have_bank[serdes_get_bank_by_lane(lane)] = 1;
 			serdes_prtcl_map |= (1 << lane_prtcl);
 		}
 	}
@@ -339,11 +543,32 @@ void fsl_serdes_init(void)
 		have_bank[FSL_SRDS_BANK_3] = 1;
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
+	/*
+	 * The work-aroud for erratum SERDES-A001 is needed only if bank two
+	 * is disabled and bank three is enabled.
+	 */
+	need_serdes_a001 =
+		!have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
+#endif
+
+	/* Power down the banks we're not interested in */
 	for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
 		if (!have_bank[bank]) {
 			printf("SERDES: bank %d disabled\n", bank + 1);
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
+			/*
+			 * Erratum SERDES-A001 says bank two needs to be powered
+			 * down after bank three is powered up, so don't power
+			 * down bank two here.
+			 */
+			if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
+				setbits_be32(&srds_regs->bank[bank].rstctl,
+					     SRDS_RSTCTL_SDPD);
+#else
 			setbits_be32(&srds_regs->bank[bank].rstctl,
 				     SRDS_RSTCTL_SDPD);
+#endif
 		}
 	}
 
@@ -369,6 +594,35 @@ void fsl_serdes_init(void)
 		printf("%s ", serdes_prtcl_str[lane_prtcl]);
 #endif
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+		/*
+		 * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
+		 * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
+		 * AURORA before the device is initialized.
+		 */
+		switch (lane_prtcl) {
+		case SGMII_FM1_DTSEC1:
+		case SGMII_FM1_DTSEC2:
+		case SGMII_FM1_DTSEC3:
+		case SGMII_FM1_DTSEC4:
+		case SGMII_FM2_DTSEC1:
+		case SGMII_FM2_DTSEC2:
+		case SGMII_FM2_DTSEC3:
+		case SGMII_FM2_DTSEC4:
+		case XAUI_FM1:
+		case XAUI_FM2:
+		case SRIO1:
+		case SRIO2:
+		case AURORA:
+			clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
+					SRDS_TTLCR0_FLT_SEL_MASK,
+					SRDS_TTLCR0_FLT_SEL_750PPM |
+					SRDS_TTLCR0_PM_DIS);
+		default:
+			break;
+		}
+#endif
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 		switch (lane_prtcl) {
 		case PCIE1:
@@ -415,13 +669,12 @@ void fsl_serdes_init(void)
 					    FSL_CORENET_DEVDISR2_DTSEC2_4;
 			break;
 		case XAUI_FM1:
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1	|
+					    FSL_CORENET_DEVDISR2_10GEC1;
+			break;
 		case XAUI_FM2:
-			if (lane_prtcl == XAUI_FM1)
-				serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1	|
-						    FSL_CORENET_DEVDISR2_10GEC1;
-			else
-				serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2	|
-						    FSL_CORENET_DEVDISR2_10GEC2;
+			serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2	|
+					    FSL_CORENET_DEVDISR2_10GEC2;
 			break;
 		case AURORA:
 			break;
@@ -436,9 +689,11 @@ void fsl_serdes_init(void)
 	puts("\n");
 #endif
 
-	for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
-		u32 rstctl;
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+	p4080_erratum_serdes_a005(srds_regs, cfg);
+#endif
 
+	for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
 		bank = idx;
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -477,18 +732,30 @@ void fsl_serdes_init(void)
 		/* reset banks for errata */
 		setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
 
-		/* wait for reset complete or 1-second timeout */
-		end_tick = usec2ticks(1000000) + get_ticks();
-		do {
-			rstctl = in_be32(&srds_regs->bank[bank].rstctl);
-			if (rstctl & SRDS_RSTCTL_RSTDONE)
-				break;
-		} while (end_tick > get_ticks());
-
-		if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
-			printf("SERDES: timeout resetting bank %d\n",
-			       bank + 1);
-			continue;
-		}
+		wait_for_rstdone(bank);
 	}
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
+	if (need_serdes_a001) {
+		/*
+		 * Bank three has been enabled, so enable bank two and then
+		 * disable it.
+		 */
+		srds_lpd_b[FSL_SRDS_BANK_2] = 0;
+		enable_bank(gur, FSL_SRDS_BANK_2);
+
+		wait_for_rstdone(FSL_SRDS_BANK_2);
+
+		/* Disable bank 2 */
+		setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
+			     SRDS_RSTCTL_SDPD);
+	}
+#endif
+
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+	for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
+		if (is_serdes_configured(device))
+			__serdes_reset_rx(srds_regs, cfg, device);
+	}
+#endif
 }
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
index 42d771e09..f261351c8 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -33,7 +33,7 @@ enum srds_bank {
 
 int is_serdes_prtcl_valid(u32 prtcl);
 int serdes_get_lane_idx(int lane);
-int serdes_get_bank(int lane);
+int serdes_get_bank_by_lane(int lane);
 int serdes_lane_enabled(int lane);
 enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
 
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index e8d53bb2f..c014163e3 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -31,6 +31,7 @@
 #include <asm/fsl_liodn.h>
 
 static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
 
 void setup_portals(void)
 {
@@ -250,3 +251,32 @@ err:
 		off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
 	}
 }
+
+void fdt_fixup_bportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	u32 rev_1 = in_be32(&bman->ip_rev_1);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+				fdt_get_name(blob, off, NULL),
+						 fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
+	}
+
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 02908b456..104d360a5 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -13,11 +13,11 @@
 #include "ddr.h"
 
 /* To avoid 64-bit full-divides, we factor this here */
-#define ULL_2e12 2000000000000ULL
-#define UL_5pow12 244140625UL
-#define UL_2pow13 (1UL << 13)
+#define ULL_2E12 2000000000000ULL
+#define UL_5POW12 244140625UL
+#define UL_2POW13 (1UL << 13)
 
-#define ULL_8Fs 0xFFFFFFFFULL
+#define ULL_8FS 0xFFFFFFFFULL
 
 /*
  * Round mclk_ps to nearest 10 ps in memory controller code.
@@ -32,7 +32,7 @@ unsigned int get_memory_clk_period_ps(void)
 	unsigned int result;
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
-	unsigned long long mclk_ps = ULL_2e12;
+	unsigned long long mclk_ps = ULL_2E12;
 
 	/* Add 5*data_rate, for rounding */
 	mclk_ps += 5*(unsigned long long)data_rate;
@@ -61,9 +61,9 @@ unsigned int picos_to_mclk(unsigned int picos)
 	 * Now divide by 5^12 and track the 32-bit remainder, then divide
 	 * by 2*(2^12) using shifts (and updating the remainder).
 	 */
-	clks_rem = do_div(clks, UL_5pow12);
+	clks_rem = do_div(clks, UL_5POW12);
 	clks_rem <<= 13;
-	clks_rem |= clks & (UL_2pow13-1);
+	clks_rem |= clks & (UL_2POW13-1);
 	clks >>= 13;
 
 	/* If we had a remainder, then round up */
@@ -71,8 +71,8 @@ unsigned int picos_to_mclk(unsigned int picos)
 		clks++;
 
 	/* Clamp to the maximum representable value */
-	if (clks > ULL_8Fs)
-		clks = ULL_8Fs;
+	if (clks > ULL_8FS)
+		clks = ULL_8FS;
 	return (unsigned int) clks;
 }
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 39a455638..e79482130 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -38,47 +38,46 @@ void print_ifc_regs(void)
 void init_early_memctl_regs(void)
 {
 #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
-	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
-	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
-
 	set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+
+	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
 
 #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
-	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
-	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
-	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
-
 	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
 	set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
 	set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
 	set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+
+	set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
+	set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
+	set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
 #endif
 
 #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
-	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
-	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
-
 	set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
 	set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
 	set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
 	set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
 
+	set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
+	set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+	set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
 #endif
 
 #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
-	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
-	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
-
 	set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
 	set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
 	set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
 	set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+
+	set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
+	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
 #endif
 }
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 624d8c2cc..9aad9be1b 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -29,6 +29,13 @@
 #include <asm/config_mpc86xx.h>
 #endif
 
+/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
+#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
+# ifndef CONFIG_HARD_SPI
+#  define CONFIG_HARD_SPI
+# endif
+#endif
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 41fd86c4e..41c2d20df 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -264,6 +264,10 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
@@ -275,6 +279,10 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
@@ -282,6 +290,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -295,6 +304,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -304,6 +314,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
+#define CONFIG_SYS_P4080_ERRATUM_SERDES9
+#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
+#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 
 /* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)
@@ -316,6 +329,10 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS			2
@@ -327,6 +344,10 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #else
 #error Processor type not defined for this platform
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 0ec5c0a3f..801571f9e 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -115,10 +115,18 @@ extern void fdt_fixup_liodn(void *blob);
 		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
 
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
 #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
 
 /* This is a bit evil since we treat rtic param as both a string & hex value */
@@ -127,6 +135,11 @@ extern void fdt_fixup_liodn(void *blob);
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
 
 #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 82d75bef6..fc47a9f7e 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -230,7 +230,9 @@ int fsl_pcie_init_board(int busno);
 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
 
-#if defined(CONFIG_FSL_CORENET)
+#if !defined(CONFIG_PCI)
+#define FT_FSL_PCI_SETUP
+#elif defined(CONFIG_FSL_CORENET)
 #define FSL_PCIE_COMPAT	"fsl,p4080-pcie"
 #define FT_FSL_PCI_SETUP \
 	FT_FSL_PCIE1_SETUP; \
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index cb32927a8..e1c1212c3 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -51,6 +51,7 @@ extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
 			  u32 *liodns, int liodn_offset);
 extern void setup_portals(void);
 extern void fdt_fixup_qportals(void *blob);
+extern void fdt_fixup_bportals(void *blob);
 
 extern struct qportal_info qp_info[];
 extern void fdt_portal(void *blob, const char *compat, const char *container,
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 85518eb6e..0f31af1db 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -53,4 +53,11 @@ enum srds_prtcl {
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
 
+#ifdef CONFIG_FSL_CORENET
+int serdes_get_first_lane(enum srds_prtcl device);
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+void serdes_reset_rx(enum srds_prtcl device);
+#endif
+#endif
+
 #endif /* __FSL_SERDES_H */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b51017b55..f85cee270 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1920,9 +1920,56 @@ typedef struct ccsr_gur {
 	u32	gpindr;		/* General-purpose input data */
 	u8	res5[12];
 	u32	pmuxcr;		/* Alt. function signal multiplex control */
+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#define MPC85xx_PMUXCR_TSEC1_0_1588		0x40000000
+#define MPC85xx_PMUXCR_TSEC1_0_RES		0xC0000000
+#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
+#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12		0x20000000
+#define MPC85xx_PMUXCR_TSEC1_1_RES		0x30000000
+#define MPC85xx_PMUXCR_TSEC1_2_DMA		0x04000000
+#define MPC85xx_PMUXCR_TSEC1_2_GPIO		0x08000000
+#define MPC85xx_PMUXCR_TSEC1_2_RES		0x0C000000
+#define MPC85xx_PMUXCR_TSEC1_3_RES		0x01000000
+#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15		0x02000000
+#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC		0x00400000
+#define MPC85xx_PMUXCR_IFC_ADDR16_USB		0x00800000
+#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB	0x00200000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
+#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
+#define MPC85xx_PMUXCR_IFC_ADDR19_USB		0x00080000
+#define MPC85xx_PMUXCR_IFC_ADDR19_DMA		0x000C0000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB	0x00020000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES	0x00030000
+#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC		0x00004000
+#define MPC85xx_PMUXCR_IFC_ADDR22_USB		0x00008000
+#define MPC85xx_PMUXCR_IFC_ADDR22_RES		0x0000C000
+#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC		0x00001000
+#define MPC85xx_PMUXCR_IFC_ADDR23_USB		0x00002000
+#define MPC85xx_PMUXCR_IFC_ADDR23_RES		0x00003000
+#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC		0x00000400
+#define MPC85xx_PMUXCR_IFC_ADDR24_USB		0x00000800
+#define MPC85xx_PMUXCR_IFC_ADDR24_RES		0x00000C00
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES		0x00000300
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB		0x00000200
+#define MPC85xx_PMUXCR_LCLK_RES			0x00000040
+#define MPC85xx_PMUXCR_LCLK_USB			0x00000080
+#define MPC85xx_PMUXCR_LCLK_IFC_CS3		0x000000C0
+#define MPC85xx_PMUXCR_SPI_RES			0x00000030
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000020
+#define MPC85xx_PMUXCR_CAN1_UART		0x00000004
+#define MPC85xx_PMUXCR_CAN1_TDM			0x00000008
+#define MPC85xx_PMUXCR_CAN1_RES			0x0000000C
+#define MPC85xx_PMUXCR_CAN2_UART		0x00000001
+#define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
+#define MPC85xx_PMUXCR_CAN2_RES			0x00000003
+#endif
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
+#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
 #define MPC85xx_PMUXCR_TDM_ENA		0x00800000
 #define MPC85xx_PMUXCR_QE0		0x00008000
 #define MPC85xx_PMUXCR_QE1		0x00004000
@@ -1944,6 +1991,31 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI		0x00000000
 #endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
+#define MPC85xx_PMUXCR2_UART_TDM		0x80000000
+#define MPC85xx_PMUXCR2_UART_RES		0xC0000000
+#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN		0x10000000
+#define MPC85xx_PMUXCR2_IRQ2_RES		0x30000000
+#define MPC85xx_PMUXCR2_IRQ3_SRESET		0x04000000
+#define MPC85xx_PMUXCR2_IRQ3_RES		0x0C000000
+#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS		0x01000000
+#define MPC85xx_PMUXCR2_GPIO01_RES		0x03000000
+#define MPC85xx_PMUXCR2_GPIO23_CKSTP		0x00400000
+#define MPC85xx_PMUXCR2_GPIO23_RES		0x00800000
+#define MPC85xx_PMUXCR2_GPIO23_USB		0x00C00000
+#define MPC85xx_PMUXCR2_GPIO4_MCP		0x00100000
+#define MPC85xx_PMUXCR2_GPIO4_RES		0x00200000
+#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT		0x00300000
+#define MPC85xx_PMUXCR2_GPIO5_UDE		0x00040000
+#define MPC85xx_PMUXCR2_GPIO5_RES		0x00080000
+#define MPC85xx_PMUXCR2_READY_ASLEEP		0x00020000
+#define MPC85xx_PMUXCR2_DDR_ECC_MUX		0x00010000
+#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
+#define MPC85xx_PMUXCR2_POST_EXPOSE		0x00004000
+#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
+#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
+#endif
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f1000
 #define MPC85xx_PMUXCR2_USB		0x00150000
@@ -2029,6 +2101,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
@@ -2065,6 +2138,9 @@ typedef struct serdes_corenet {
 #define SRDS_TECR0_TEQ_TYPE_2LVL	0x10000000
 		u32	res3;
 		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
+#define SRDS_TTLCR0_FLT_SEL_MASK	0x3f000000
+#define SRDS_TTLCR0_FLT_SEL_750PPM	0x03000000
+#define SRDS_TTLCR0_PM_DIS		0x00004000
 		u32	res4[7];
 	} lane[24];
 	u32 res6[384];
@@ -2213,6 +2289,13 @@ typedef struct ccsr_pme {
 	u8	res4[0x400];
 } ccsr_pme_t;
 
+typedef struct ccsr_usb_phy {
+	u8	res0[0x18];
+	u32	usb_enable_override;
+	u8	res[0xe4];
+} ccsr_usb_phy_t;
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
@@ -2235,6 +2318,8 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		CONFIG_SYS_MPC85xx_USB1_OFFSET
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
@@ -2357,6 +2442,10 @@ typedef struct ccsr_pme {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \