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authorTom Rini <trini@ti.com>2012-07-24 14:55:38 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-05 22:02:39 +0200
commit94fbd7342999ee28620919ebeee13087507060a4 (patch)
tree0fca603d05cadaec83dd7fb90d948eb78ddec400 /arch
parent45d6adee31b2c402e26f470125b84cb0023a6131 (diff)
downloadu-boot-linaro-stable-94fbd7342999ee28620919ebeee13087507060a4.tar.gz
am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c28
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c43
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h38
3 files changed, 31 insertions, 78 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 7ac144a98..993f3da00 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -42,33 +42,33 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
/**
* Configure SDRAM
*/
-void config_sdram(struct sdram_config *cfg)
+void config_sdram(const struct emif_regs *regs)
{
- writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
- writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
- writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+ writel(regs->sdram_config, &emif_reg->emif_sdram_config);
}
/**
* Set SDRAM timings
*/
-void set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(const struct emif_regs *regs)
{
- writel(t->time1, &emif_reg->emif_sdram_tim_1);
- writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
- writel(t->time2, &emif_reg->emif_sdram_tim_2);
- writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
- writel(t->time3, &emif_reg->emif_sdram_tim_3);
- writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
+ writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+ writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+ writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+ writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+ writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+ writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
}
/**
* Configure DDR PHY
*/
-void config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(const struct emif_regs *regs)
{
- writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
- writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
}
/**
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 66ab892bf..0190ec65e 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -90,6 +90,15 @@ static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = DDR2_EMIF_SDCFG,
+ .ref_ctrl = DDR2_EMIF_SDREF,
+ .sdram_tim1 = DDR2_EMIF_TIM1,
+ .sdram_tim2 = DDR2_EMIF_TIM2,
+ .sdram_tim3 = DDR2_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -105,35 +114,6 @@ static void config_vtp(void)
;
}
-static void config_emif_ddr2(void)
-{
- struct sdram_config cfg;
- struct sdram_timing tmg;
- struct ddr_phy_control phyc;
-
- /* Program EMIF0 CFG Registers */
- phyc.reg = DDR2_EMIF_READ_LATENCY;
- phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
- phyc.reg2 = DDR2_EMIF_READ_LATENCY;
-
- tmg.time1 = DDR2_EMIF_TIM1;
- tmg.time1_sh = DDR2_EMIF_TIM1;
- tmg.time2 = DDR2_EMIF_TIM2;
- tmg.time2_sh = DDR2_EMIF_TIM2;
- tmg.time3 = DDR2_EMIF_TIM3;
- tmg.time3_sh = DDR2_EMIF_TIM3;
-
- cfg.sdrcr = DDR2_EMIF_SDCFG;
- cfg.sdrcr2 = DDR2_EMIF_SDCFG;
- cfg.refresh = DDR2_EMIF_SDREF;
- cfg.refresh_sh = DDR2_EMIF_SDREF;
-
- /* Program EMIF instance */
- config_ddr_phy(&phyc);
- set_sdram_timings(&tmg);
- config_sdram(&cfg);
-}
-
void config_ddr(short ddr_type)
{
struct ddr_ioctrl ioctrl;
@@ -163,7 +143,10 @@ void config_ddr(short ddr_type)
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- config_emif_ddr2();
+ /* Program EMIF instance */
+ config_ddr_phy(&ddr2_emif_reg_data);
+ set_sdram_timings(&ddr2_emif_reg_data);
+ config_sdram(&ddr2_emif_reg_data);
}
}
#endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 997480bae..7806e1b92 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -20,6 +20,7 @@
#define _DDR_DEFS_H
#include <asm/arch/hardware.h>
+#include <asm/emif.h>
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
@@ -49,50 +50,19 @@
#define DDR2_IOCTRL_VALUE 0x18B
/**
- * Encapsulates DDR PHY control and corresponding shadow registers.
- */
-struct ddr_phy_control {
- unsigned long reg;
- unsigned long reg_sh;
- unsigned long reg2;
-};
-
-/**
- * Encapsulates SDRAM timing and corresponding shadow registers.
- */
-struct sdram_timing {
- unsigned long time1;
- unsigned long time1_sh;
- unsigned long time2;
- unsigned long time2_sh;
- unsigned long time3;
- unsigned long time3_sh;
-};
-
-/**
- * Encapsulates SDRAM configuration.
- * (Includes refresh control registers) */
-struct sdram_config {
- unsigned long sdrcr;
- unsigned long sdrcr2;
- unsigned long refresh;
- unsigned long refresh_sh;
-};
-
-/**
* Configure SDRAM
*/
-void config_sdram(struct sdram_config *cfg);
+void config_sdram(const struct emif_regs *regs);
/**
* Set SDRAM timings
*/
-void set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(const struct emif_regs *regs);
/**
* Configure DDR PHY
*/
-void config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(const struct emif_regs *regs);
/**
* This structure represents the DDR registers on AM33XX devices.