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authorTom Rini <trini@ti.com>2012-07-30 16:13:10 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-05 22:02:39 +0200
commit40039736f150348d61d27ffa55db65a087d249a7 (patch)
tree800c5e07e105bc7feec80fb21e6c9f12ea2c36ea /arch
parentd0adb945e64ee7f31c34dc712cf5658e231b6688 (diff)
downloadu-boot-linaro-stable-40039736f150348d61d27ffa55db65a087d249a7.tar.gz
am33xx: Remove board/ti/am335x/evm.c
The intention has always been (and boards are to support) an i2c EEPROM that will identify what hardware they are, allowing a single binary to support multiple boards. As such, remove the 'evm.c' file as there is nothing EVM centric in it currently, only SoC peripheral configuration. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c173
1 files changed, 173 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index ec542fd05..4634a9ab4 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -17,6 +17,7 @@
*/
#include <common.h>
+#include <errno.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
@@ -28,6 +29,9 @@
#include <asm/io.h>
#include <asm/omap_common.h>
#include <asm/emif.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +48,79 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+/* MII mode defines */
+#define MII_MODE_ENABLE 0x0
+#define RGMII_MODE_ENABLE 0xA
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * I2C Address of on-board EEPROM
+ */
+#define I2C_BASE_BOARD_ADDR 0x50
+
+#define NO_OF_MAC_ADDR 3
+#define ETH_ALEN 6
+#define NAME_LEN 8
+
+struct am335x_baseboard_id {
+ unsigned int magic;
+ char name[NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[NO_OF_MAC_ADDR][ETH_ALEN];
+};
+
+static struct am335x_baseboard_id header;
+
+static inline int board_is_bone(void)
+{
+ return !strncmp(header.name, "A335BONE", NAME_LEN);
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(I2C_BASE_BOARD_ADDR)) {
+ puts("Could not probe the EEPROM; something fundamentally "
+ "wrong on the I2C bus.\n");
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 2, (uchar *)&header,
+ sizeof(header))) {
+ puts("Could not read the EEPROM; something fundamentally"
+ " wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header.magic != 0xEE3355AA) {
+ /*
+ * read the eeprom using i2c again,
+ * but use only a 1 byte address
+ */
+ if (i2c_read(I2C_BASE_BOARD_ADDR, 0, 1, (uchar *)&header,
+ sizeof(header))) {
+ puts("Could not read the EEPROM; something "
+ "fundamentally wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header.magic != 0xEE3355AA) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header.magic);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
@@ -127,3 +204,99 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
+
+/*
+ * Basic board specific setup
+ */
+int board_init(void)
+{
+ enable_uart0_pin_mux();
+
+ enable_i2c0_pin_mux();
+ enable_i2c1_pin_mux();
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = AM335X_CPSW_MDIO_BASE,
+ .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ debug("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ return -1;
+ }
+
+ if (board_is_bone()) {
+ enable_mii1_pin_mux();
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_MII;
+ } else {
+ enable_rgmii1_pin_mux();
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_RGMII;
+ }
+
+ return cpsw_register(&cpsw_data);
+}
+#endif