diff options
| author | Sebastien Jan <s-jan@ti.com> | 2011-10-04 09:22:13 +0200 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2012-01-19 12:54:19 -0700 |
| commit | 734ce05704d3dd7b5eff37d2c6a1653458dcceba (patch) | |
| tree | 46b87eaa05af0cd6812d78481532f7f927a57879 /arch | |
| parent | c04c33c905b4eb877b4b8891d903c60f4f142ebf (diff) | |
omap4: reduce default operating point for 4460 devices
Reduce the operating point for 4460 to OPP100 (MPU at 700MHz)
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 6c427aba9..a1bb00fbe 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -67,15 +67,15 @@ const u32 sys_clk_array[8] = { * Please use this tool for creating the table for any new frequency. */ -/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ -static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { - {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100 4460) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ @@ -203,7 +203,7 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params) * Resulting MPU frequencies: * 4430 ES1.0 : 600 MHz * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled + * 4460 : 700 MHz (OPP 100) - DCC disabled */ const struct dpll_params *get_mpu_dpll_params(void) { @@ -217,7 +217,7 @@ const struct dpll_params *get_mpu_dpll_params(void) else if (omap_rev < OMAP4460_ES1_0) return &mpu_dpll_params_1600mhz[sysclk_ind]; else - return &mpu_dpll_params_1840mhz[sysclk_ind]; + return &mpu_dpll_params_1400mhz[sysclk_ind]; } const struct dpll_params *get_core_dpll_params(void) |