diff options
| author | Chander Kashyap <chander.kashyap@linaro.org> | 2011-12-18 22:56:44 +0000 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2012-01-19 17:08:47 -0700 |
| commit | 0d96deb171412f437a4def028084e3b114f10039 (patch) | |
| tree | 2d58fe28144f67f452cb434423d263ff2f58b4a0 /arch | |
| parent | 25bee73d9cd161847d921ef456dccd026b03b377 (diff) | |
Exynos: Fix ARM Clock frequency calculation
Earliar ARM clock frequency was calculated by:
MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
It is fixed by calculating it as follows:
ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1)
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 64de26273..0c199cdab 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -102,17 +102,20 @@ static unsigned long exynos4_get_arm_clk(void) struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned long div; - unsigned long dout_apll; - unsigned int apll_ratio; + unsigned long armclk; + unsigned int core_ratio; + unsigned int core2_ratio; div = readl(&clk->div_cpu0); - /* APLL_RATIO: [26:24] */ - apll_ratio = (div >> 24) & 0x7; + /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ + core_ratio = (div >> 0) & 0x7; + core2_ratio = (div >> 28) & 0x7; - dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + armclk = get_pll_clk(APLL) / (core_ratio + 1); + armclk /= (core2_ratio + 1); - return dout_apll; + return armclk; } /* exynos4: return pwm clock frequency */ |