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authorMike Williams <mike@mikebwilliams.com>2011-07-22 04:01:30 +0000
committerWolfgang Denk <wd@denx.de>2011-07-28 21:27:36 +0200
commit1626308797ac4184e73e56d275a1b8da11a62d5b (patch)
treed12fd0d610303c3d2351d8ace314a643f20e0fc9 /arch/powerpc/include/asm/ppc440sp.h
parent2469c4b2dbdd601a4e44ecf9925b99bd2cd1b43f (diff)
cleanup: Fix typos and misspellings in various files.
Recieve/Receive recieve/receive Interupt/Interrupt interupt/interrupt Addres/Address addres/address Signed-off-by: Mike Williams <mike@mikebwilliams.com>
Diffstat (limited to 'arch/powerpc/include/asm/ppc440sp.h')
-rw-r--r--arch/powerpc/include/asm/ppc440sp.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
index 4387495cd..cc2ff6812 100644
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -67,7 +67,7 @@
#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
-#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
+#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
#define PRADV_MASK 0x07000000 /* Primary Divisor A */
#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
@@ -77,7 +77,7 @@
#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
-#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */