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authorStefan Roese <sr@denx.de>2010-09-20 16:05:31 +0200
committerStefan Roese <sr@denx.de>2010-09-23 09:02:05 +0200
commit550650ddd0fde00f245bc3da72d7272844198394 (patch)
tree6a9ef8ac54cfaf5ff63a047b2c66d0e058e4cd9f /arch/powerpc/include/asm/ppc405ez.h
parentafabb498b749b48ca3ee7e833fe1501e2d6993cb (diff)
ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/include/asm/ppc405ez.h')
-rw-r--r--arch/powerpc/include/asm/ppc405ez.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/ppc405ez.h b/arch/powerpc/include/asm/ppc405ez.h
index 9192c6281..cb8e994b2 100644
--- a/arch/powerpc/include/asm/ppc405ez.h
+++ b/arch/powerpc/include/asm/ppc405ez.h
@@ -24,8 +24,13 @@
#define CONFIG_NAND_NDFC
/* Memory mapped register */
-#define GPIO0_BASE 0xef600700
-#define GPIO1_BASE 0xef600800
+#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
/* DCR register */
#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */