diff options
| author | Tom Rini <trini@ti.com> | 2012-10-22 16:54:38 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-22 16:54:38 -0700 |
| commit | c7656bab411433f987baa2288eff8c78ddc0f378 (patch) | |
| tree | 18fe8fa515ecdea19afa83d1af0c6eff4946a5d4 /arch/powerpc/include/asm/fsl_ddr_sdram.h | |
| parent | bdc3ff6e4f75813d01e51081799d10e4a9c7fbcb (diff) | |
| parent | 23028d69e950023a3cb605751dbcb1e314be8b36 (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include/asm/fsl_ddr_sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index e271342f0..640d3297d 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D +#define SDRAM_CS_CONFIG_EN 0x80000000 + /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 @@ -96,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 @@ -145,6 +148,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { @@ -177,6 +205,8 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; @@ -262,6 +292,8 @@ typedef struct memctl_options_s { unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; unsigned int twoT_en; @@ -288,6 +320,7 @@ typedef struct memctl_options_s { unsigned int rcw_2; /* control register 1 */ unsigned int ddr_cdr1; + unsigned int ddr_cdr2; unsigned int trwt_override; unsigned int trwt; /* read-to-write turnaround */ @@ -298,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void); extern int fsl_use_spd(void); extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); +u32 fsl_ddr_get_intl3r(void); /* * The 85xx boards have a common prototype for fixed_sdram so put the |