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authorYork Sun <yorksun@freescale.com>2012-08-17 08:22:37 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:55 -0500
commit73b5396b25c52463aa71c782316e2d77a4b8d5ed (patch)
treeb6e82b205f1dc1a2d4a1eac37ec136cbe22822fa /arch/powerpc/include/asm/fsl_ddr_dimm_params.h
parent744713a6a3ca19c77585a9452829a2e2a55693ad (diff)
downloadu-boot-linaro-stable-73b5396b25c52463aa71c782316e2d77a4b8d5ed.tar.gz
powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_ddr_dimm_params.h')
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_dimm_params.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 982b80946..ffe4db8b8 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -43,6 +43,7 @@ typedef struct dimm_params_s {
/* DIMM timing parameters */
unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
+ unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
unsigned int tFAW_ps; /* four active window delay, only for ddr3 */