diff options
| author | York Sun <yorksun@freescale.com> | 2011-11-20 10:01:35 -0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-11-29 08:48:06 -0600 |
| commit | 4108508a96972e1200867666890d19fb63f76025 (patch) | |
| tree | 075274001cf896c4bc9208b978204fb2ac483cdd /arch/powerpc/include/asm/config_mpc85xx.h | |
| parent | 33c875366e1d3e433881a86704816cdad847532f (diff) | |
powerpc/85xx: Add workaround for erratum A-003474
Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.
Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
CCSRBAR + DDR OFFSET + 0xf54
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/config_mpc85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f1da82eba..2e4be3436 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -314,6 +314,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -333,6 +334,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -352,6 +354,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -379,6 +382,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -408,6 +412,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -427,6 +432,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -445,6 +451,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #else #error Processor type not defined for this platform |