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authorBecky Bruce <beckyb@kernel.crashing.org>2010-06-17 11:37:20 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:09 -0500
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /arch/powerpc/cpu/mpc86xx
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
downloadu-boot-linaro-stable-f51cdaf19141151ce2b40d562a468605340f2315.tar.gz
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx')
-rw-r--r--arch/powerpc/cpu/mpc86xx/cpu.c15
-rw-r--r--arch/powerpc/cpu/mpc86xx/cpu_init.c55
-rw-r--r--arch/powerpc/cpu/mpc86xx/speed.c5
3 files changed, 3 insertions, 72 deletions
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index 9064e7803..4e90fd220 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -180,22 +180,9 @@ watchdog_reset(void)
*/
void mpc86xx_reginfo(void)
{
- immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- ccsr_lbc_t *lbc = &immap->im_lbc;
-
print_bats();
print_laws();
-
- printf ("Local Bus Controller Registers\n"
- "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
- printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
- printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
- printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
- printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
- printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
- printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
- printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
-
+ print_lbc_regs();
}
/*
diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c
index b4f047d85..82c216ba5 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c
@@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
-
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -61,58 +58,8 @@ void cpu_init_f(void)
setup_bats();
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
-
-#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->or0 = CONFIG_SYS_OR0_REMAP;
-#endif
-#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->or1 = CONFIG_SYS_OR1_REMAP;
-#endif
-
- /* now restrict to preliminary range */
-#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
- memctl->br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->or0 = CONFIG_SYS_OR0_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- memctl->or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->br1 = CONFIG_SYS_BR1_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- memctl->or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->br2 = CONFIG_SYS_BR2_PRELIM;
-#endif
+ init_early_memctl_regs();
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- memctl->or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->br3 = CONFIG_SYS_BR3_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- memctl->or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->br4 = CONFIG_SYS_BR4_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- memctl->or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->br5 = CONFIG_SYS_BR5_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- memctl->or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->br6 = CONFIG_SYS_BR6_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- memctl->or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->br7 = CONFIG_SYS_BR7_PRELIM;
-#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 64a3479d7..a2d0a8ac6 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
- {
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
- }
+ lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);