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authorAneesh V <aneesh@ti.com>2011-11-21 23:34:01 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-06 23:59:34 +0100
commite4fce34e7a5f484de2ca557fd43a198fd14894b7 (patch)
treef98e9c4d5d677836de688e37ea0cfe3b57b6a98c /arch/arm/cpu/armv7/omap3/lowlevel_init.S
parenta8c686399f01c359713447c2adaecf94f3a4445b (diff)
downloadu-boot-linaro-stable-e4fce34e7a5f484de2ca557fd43a198fd14894b7.tar.gz
start.S: remove omap3 specific code from start.S
Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/lowlevel_init.S')
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index a308ebdb6..2f6930b22 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -216,6 +216,14 @@ lowlevel_init:
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+/*
+ * No need to copy/exec the clock code - DPLL adjust already done
+ * in NAND/oneNAND Boot.
+ */
+ ldr r1, =SRAM_CLK_CODE
+ bl cpy_clk_code
+#endif /* NAND Boot */
bl s_init /* go setup pll, mux, memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */