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authorAneesh V <aneesh@ti.com>2011-06-16 23:30:53 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-07-04 10:55:25 +0200
commit45bf05854bc94ed8bae9e9114292895b990327ea (patch)
tree1bc119e00d0dd4a58b36df51cc07768a950352a0 /arch/arm/cpu/armv7/omap3/lowlevel_init.S
parent8b457fa828971ac036b15e98e65d99b6354c5496 (diff)
downloadu-boot-linaro-stable-45bf05854bc94ed8bae9e9114292895b990327ea.tar.gz
armv7: adapt omap3 to the new cache maintenance framework
adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/lowlevel_init.S')
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 14580729b..67e8ceb55 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -35,6 +35,38 @@
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
+.global omap3_gp_romcode_call
+omap3_gp_romcode_call:
+ PUSH {r4-r12, lr} @ Save all registers from ROM code!
+ MOV r12, r0 @ Copy the Service ID in R12
+ MOV r0, r1 @ Copy parameter to R0
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c10, 5 @ DMB
+ .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
+ @ because we use -march=armv5
+ POP {r4-r12, pc}
+
+/*
+ * Funtion for making PPA HAL API calls in secure devices
+ * Input:
+ * R0 - Service ID
+ * R1 - paramer list
+ */
+.global do_omap3_emu_romcode_call
+do_omap3_emu_romcode_call:
+ PUSH {r4-r12, lr} @ Save all registers from ROM code!
+ MOV r12, r0 @ Copy the Secure Service ID in R12
+ MOV r3, r1 @ Copy the pointer to va_list in R3
+ MOV r1, #0 @ Process ID - 0
+ MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
+ @ to va_list in R3
+ MOV r6, #0xFF @ Indicate new Task call
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c10, 5 @ DMB
+ .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
+ @ because we use -march=armv5
+ POP {r4-r12, pc}
+
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
* cpy_clk_code: relocates clock code into SRAM where its safer to execute