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authorYork Sun <yorksun@freescale.com>2012-05-07 07:39:53 +0000
committerAndy Fleming <afleming@freescale.com>2012-07-06 17:30:33 -0500
commitfeae34243f63fc319b40db7b92070a0718dc31a6 (patch)
treec5b580dd44864faf5cfc586e42edb3c30a3ed110
parent5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6 (diff)
downloadu-boot-linaro-stable-feae34243f63fc319b40db7b92070a0718dc31a6.tar.gz
powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 36c79d363..1860684c1 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -171,15 +171,12 @@ __secondary_start_page:
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
- mfspr r2,SPRN_SVR
+ mfspr r3,SPRN_SVR
+ rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
+
lis r3,SVR_P2040@h
ori r3,r3,SVR_P2040@l
- cmpw r2,r3
- beq 3f
-
- lis r3,SVR_P2040_E@h
- ori r3,r3,SVR_P2040_E@l
- cmpw r2,r3
+ cmpw r6,r3
beq 3f
/* Enable/invalidate the L2 cache */