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authorMarek Vasut <marex@denx.de>2012-07-06 21:25:57 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-14 00:36:29 +0200
commit8d49cbbffabc84710dc006a8bdcc4d29e415dbbe (patch)
tree49f965a5f9810621b9825ae93713b165f7992c94
parentd47fccf40e657e5a45559ec34d0b2381a6a9cd17 (diff)
downloadu-boot-linaro-stable-8d49cbbffabc84710dc006a8bdcc4d29e415dbbe.tar.gz
MX28: Fix MXS MMC DMA issues
The DMA didn't work properly because the DMA descriptor wasn't properly cleaned after it was used once. Also, the DMA_ENABLE bit was enabled/disabled too late. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
-rw-r--r--drivers/mmc/mxsmmc.c34
1 files changed, 19 insertions, 15 deletions
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index c2aa4aa6f..018939f8c 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -97,6 +97,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
uint32_t data_count = data->blocksize * data->blocks;
uint32_t cache_data_count;
int dmach;
+ struct mxs_dma_desc *desc = priv->desc;
+
+ memset(desc, 0, sizeof(struct mxs_dma_desc));
+ desc->address = (dma_addr_t)desc;
if (data_count % ARCH_DMA_MINALIGN)
cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
@@ -118,7 +122,6 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
-
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
mxs_dma_desc_append(dmach, priv->desc);
if (mxs_dma_go(dmach))
@@ -183,6 +186,11 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
ctrl0 |= SSP_CTRL0_LONG_RESP;
+ if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+ else
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+
/* Command index */
reg = readl(&ssp_regs->hw_ssp_cmd0);
reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
@@ -264,17 +272,6 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
return 0;
if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
- writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
-
- ret = mxsmmc_send_cmd_dma(priv, data);
- if (ret) {
- printf("MMC%d: DMA transfer failed\n",
- mmc->block_dev.dev);
- return ret;
- }
- } else {
- writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
-
ret = mxsmmc_send_cmd_pio(priv, data);
if (ret) {
printf("MMC%d: Data timeout with command %d "
@@ -282,6 +279,13 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
mmc->block_dev.dev, cmd->cmdidx, reg);
return ret;
}
+ } else {
+ ret = mxsmmc_send_cmd_dma(priv, data);
+ if (ret) {
+ printf("MMC%d: DMA transfer failed\n",
+ mmc->block_dev.dev);
+ return ret;
+ }
}
/* Check data errors */
@@ -336,9 +340,9 @@ static int mxsmmc_init(struct mmc *mmc)
/* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
- SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
- SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
- SSP_CTRL1_DMA_ENABLE);
+ SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
+ SSP_CTRL1_DMA_ENABLE,
+ SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
/* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400);