aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMarek Vasut <marex@denx.de>2012-07-06 21:25:54 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-14 00:36:29 +0200
commit440df478df749bae4ebf79316e101e936d62bcc7 (patch)
treedc7b9653c14d080c1d4e3ec13851c100dea1517c
parentfd0f8558438a57b5a1dd850476c354a3980a51f1 (diff)
downloadu-boot-linaro-stable-440df478df749bae4ebf79316e101e936d62bcc7.tar.gz
MX28: Fix up the MMC driver DMA mode
The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1. Also, it was using SSP0 DMA channel for all SSP devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
-rw-r--r--drivers/mmc/mxsmmc.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index b7ad9ca0e..2480a8a87 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -79,6 +79,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
uint32_t *data_ptr;
#else
uint32_t cache_data_count;
+ int dmach;
#endif
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
@@ -201,6 +202,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
timeout = MXSMMC_MAX_TIMEOUT;
#ifdef CONFIG_MXS_MMC_DMA
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+
if (data_count % ARCH_DMA_MINALIGN)
cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
else
@@ -222,8 +225,9 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
- mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
- if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
+ mxs_dma_desc_append(dmach, priv->desc);
+ if (mxs_dma_go(dmach)) {
printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
return COMM_ERR;
}
@@ -234,6 +238,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
(uint32_t)(priv->desc->cmd.address + cache_data_count));
}
#else
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+
if (data->flags & MMC_DATA_READ) {
data_ptr = (uint32_t *)data->dest;
while (data_count && --timeout) {