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authorJohn Rigby <john.rigby@linaro.org>2011-09-22 21:55:14 -0600
committerJohn Rigby <john.rigby@linaro.org>2012-08-16 10:10:11 -0600
commit392394a665174f9bbf79b318223116d9a77e0b03 (patch)
tree3b21907bbc58c35e0a8bdbb4216a1894484b4641
parentdb1d3d55cc02cd63f42e023490c5027b25d2334c (diff)
downloadu-boot-linaro-stable-392394a665174f9bbf79b318223116d9a77e0b03.tar.gz
SAUCE: HACK: move omap spl base address
Move NON_SECURE_SRAM_START from 0x40304000 to 0x40303000 and move u-boot-spl load address from 0x40304350 to 0x40303080. This allows it to stay under 0x4030c000 which is what the TRM says it must do. SRAM actually starts at 0x40300000 on GP devices but was set to 0x40304000 to be the same as Secure devices so this breaks that. Signed-off-by: John Rigby <john.rigby@linaro.org>
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h2
-rw-r--r--include/configs/omap4_common.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 03bd92314..f536055f5 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -167,7 +167,7 @@ struct control_lpddr2io_regs {
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
-#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_START 0x40303000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 574bba1eb..8fe2b552f 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -280,7 +280,7 @@
/* Defines for SPL */
#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_TEXT_BASE 0x40303080
#define CONFIG_SPL_MAX_SIZE (38 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK