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authorEnric Balletbò i Serra <eballetbo@gmail.com>2012-08-05 00:55:56 +0000
committerTom Rini <trini@ti.com>2012-08-07 10:07:22 -0700
commit210044a6558eaf0525c167474700832723560d66 (patch)
tree3a3fe5c9bb775cdbe4b6ef2c5363d51b82ccd83b
parent8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08 (diff)
downloadu-boot-linaro-stable-210044a6558eaf0525c167474700832723560d66.tar.gz
OMAP3: fix DRAM size for IGEP-based boards.
The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the LPDDR memory consist on two dies of 256MiB. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
-rw-r--r--board/isee/igep0020/igep0020.c6
-rw-r--r--board/isee/igep0030/igep0030.c6
2 files changed, 6 insertions, 6 deletions
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index a4d099a5d..a8257a300 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -77,19 +77,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
{
*mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
- *mcfg = MICRON_V_MCFG_200(512 << 20);
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ *mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
- *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+ *mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 4f8b6452d..107cb7f8e 100644
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -64,19 +64,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
{
*mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
- *mcfg = MICRON_V_MCFG_200(512 << 20);
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ *mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
- *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+ *mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;