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authorStefan Roese <sr@denx.de>2005-08-04 17:09:16 +0200
committerStefan Roese <sr@denx.de>2005-08-04 17:09:16 +0200
commit17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa (patch)
tree2c5d47cd55f487f0504458908d587e9bcd6963a6
parent3e0bc4473add883fd68a49b7dab971191b943415 (diff)
downloadu-boot-linaro-stable-17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa.tar.gz
Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
-rw-r--r--CHANGELOG5
-rw-r--r--board/amcc/bamboo/Makefile2
-rw-r--r--board/amcc/bamboo/bamboo.c1798
-rw-r--r--board/amcc/bamboo/bamboo.h401
-rw-r--r--board/amcc/bamboo/config.mk10
-rw-r--r--board/amcc/bamboo/flash.c166
-rw-r--r--board/amcc/bamboo/init.S2
-rw-r--r--board/amcc/bamboo/u-boot.lds5
-rw-r--r--board/amcc/common/flash.c370
-rw-r--r--cpu/ppc4xx/405gp_enet.c27
-rw-r--r--cpu/ppc4xx/440gx_enet.c63
-rw-r--r--cpu/ppc4xx/cpu.c4
-rw-r--r--cpu/ppc4xx/spd_sdram.c16
-rw-r--r--cpu/ppc4xx/start.S8
-rw-r--r--include/440gx_enet.h27
-rw-r--r--include/configs/bamboo.h271
-rw-r--r--include/ppc440.h152
17 files changed, 3005 insertions, 322 deletions
diff --git a/CHANGELOG b/CHANGELOG
index e4651e7fc..326eaa753 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,11 +2,14 @@
Changes for U-Boot 1.1.3:
======================================================================
+* Add support for AMCC Bamboo PPC440EP eval board
+ Patch by Stefan Roese, 04 Aug 2005
+
* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
routed to the Watchdog handler
Patch by Eugene Surovegin, 18 Jun 2005
-* (re)enabled scsi commands do_scsi() and do_scsiboot()
+* (re)enabled scsi commands do_scsi() and do_scsiboot()
Patch by Denis Peter, 06 Dec 2004
* Fix endianess problem in TFTP / NFS default filenames
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
index 0b9790607..5654f91a8 100644
--- a/board/amcc/bamboo/Makefile
+++ b/board/amcc/bamboo/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
-#OBJS += flash.o
+OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 7b2d3f4c3..a3c702473 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -24,40 +24,193 @@
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
+#include <ppc440.h>
+#include "bamboo.h"
-int board_early_init_f(void)
-{
- register uint reg;
+void ext_bus_cntlr_init(void);
+void configure_ppc440ep_pins(void);
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr(ebccfga, xbcfg);
- reg = mfdcr(ebccfgd);
- mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
+#if 0
+{ /* GPIO Alternate1 Alternate2 Alternate3 */
+ {
+ /* GPIO Core 0 */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
+ { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
+ },
+ {
+ /* GPIO Core 1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+ }
+};
+#endif
-#if 0 /* test-only */
- mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
+/*----------------------------------------------------------------------------+
+ | EBC Devices Characteristics
+ | Peripheral Bank Access Parameters - EBC0_BnAP
+ | Peripheral Bank Configuration Register - EBC0_BnCR
+ +----------------------------------------------------------------------------*/
+/* Small Flash */
+#define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(6) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(3) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
- mtebc(pb1ap, 0x00000000);
- mtebc(pb1cr, 0x00000000);
+#define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
- mtebc(pb2ap, 0x04814500);
- /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
-#else
- mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
-#endif
+#define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+/* Large Flash or SRAM */
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(8) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(1) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
- mtebc(pb3ap, 0x00000000);
- mtebc(pb3cr, 0x00000000);
+/* NVRAM - FPGA */
+#define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(9) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
- mtebc(pb4ap, 0x00000000);
- mtebc(pb4cr, 0x00000000);
+#define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
- mtebc(pb5ap, 0x00000000);
- mtebc(pb5cr, 0x00000000);
+/* Nand Flash */
+#define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(3) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(0) | \
+ EBC0_BNAP_WBN_ENCODE(0) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_NOT_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+
+#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
+
+/* NAND0 */
+#define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+/* NAND1 - Bank2 */
+#define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+/* NAND1 - Bank3 */
+#define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+int board_early_init_f(void)
+{
+ ext_bus_cntlr_init();
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -81,52 +234,29 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
- /*CPLD cs */
- /*setup Address lines for flash sizes larger than 16Meg. */
- out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
-
- /*setup emac */
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
- out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
- out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
- out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
- /*UART1 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
- out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
-
- /*setup USB 2.0 */
- out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
- out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
- out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
- out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
-
- /*--------------------------------------------------------------------
- * Setup other serial configuration
- *-------------------------------------------------------------------*/
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
- mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
-
-#if 0 /* test-only */
- /*clear tmrclk divisor */
- *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
-
- /*enable ethernet */
- *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+ out32(GPIO0_OSRL, 0x00000400);
+ out32(GPIO0_OSRH, 0x00000000);
+ out32(GPIO0_TSRL, 0x00000400);
+ out32(GPIO0_TSRH, 0x00000000);
+ out32(GPIO0_ISR1L, 0x00000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000000);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
- /*enable usb 1.1 fs device and remove usb 2.0 reset */
- *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+ out32(GPIO1_OSRL, 0x0C380000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x0C380000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x0FC30000);
+ out32(GPIO1_ISR1H, 0x00000000);
+ out32(GPIO1_ISR2L, 0x0C010000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x01400000);
+ out32(GPIO1_ISR3H, 0x00000000);
- /*get rid of flash write protect */
- *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
-#endif
+ configure_ppc440ep_pins();
return 0;
}
@@ -150,31 +280,35 @@ int checkboard(void)
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
return (0);
}
/*************************************************************************
- * sdram_init -- doesn't use serial presence detect.
*
- * Assumes: 256 MB, ECC, non-registered
+ * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ * 13 row add bits, 10 column add bits (but 12 row used only).
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ * 12 row add bits, 10 column add bits.
+ * Prepare a subset (only the used ones) of SPD data
+ *
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ * the corresponding bank is divided by 2 due to number of Row addresses
+ * 12 in the ECC module
+ *
+ * Assumes: 64 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
-void sdram_init(void)
+void fixed_sdram_init(void)
{
- register uint reg;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_clktr, 0x40000000); /* ?? */
- mtsdram(mem_wddctr, 0x40000000); /* ?? */
-
- /*clear this first, if the DDR is enabled by a debugger
- then you can not make changes. */
+ /*
+ * clear this first, if the DDR is enabled by a debugger
+ * then you can not make changes.
+ */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
@@ -183,36 +317,23 @@ void sdram_init(void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
-
- mtsdram(mem_tr0, 0x410a4012); /* ?? */
- mtsdram(mem_tr1, 0x8080080b); /* ?? */
- mtsdram(mem_rtr, 0x04080000); /* ?? */
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
- udelay(400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
-
- for (;;) {
- mfsdram(mem_mcsts, reg);
- if (reg & 0x80000000)
- break;
- }
+ mtsdram(mem_b0cr, 0x00082001);
+ mtsdram(mem_b1cr, 0x00000000);
+ mtsdram(mem_b2cr, 0x00000000);
+ mtsdram(mem_b3cr, 0x00000000);
}
-/*************************************************************************
- * long int initdram
- *
- ************************************************************************/
-long int initdram(int board)
+long int initdram (int board_type)
{
- sdram_init();
- return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
+ long dram_size = 0;
+
+ /*
+ * First init bank0 (onboard sdram) and then configure the DIMM-slots
+ */
+ fixed_sdram_init();
+ dram_size = spd_sdram (0);
+
+ return dram_size;
}
#if defined(CFG_DRAM_TEST)
@@ -425,15 +546,1450 @@ int is_pci_host(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * hw_watchdog_reset
- *
- * This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
+/*----------------------------------------------------------------------------+
+ | is_powerpc440ep_pass1.
+ +----------------------------------------------------------------------------*/
+int is_powerpc440ep_pass1(void)
+{
+ unsigned long pvr;
+
+ pvr = get_pvr();
+
+ if (pvr == PVR_POWERPC_440EP_PASS1)
+ return TRUE;
+ else if (pvr == PVR_POWERPC_440EP_PASS2)
+ return FALSE;
+ else {
+ printf("brdutil error 3\n");
+ for (;;)
+ ;
+ }
+
+ return(FALSE);
+}
+
+/*----------------------------------------------------------------------------+
+ | is_nand_selected.
+ +----------------------------------------------------------------------------*/
+int is_nand_selected(void)
+{
+ return FALSE; /* test-only */
+}
+
+/*----------------------------------------------------------------------------+
+ | config_on_ebc_cs4_is_small_flash => from EPLD
+ +----------------------------------------------------------------------------*/
+unsigned char config_on_ebc_cs4_is_small_flash(void)
+{
+ /* Not implemented yet => returns constant value */
+ return TRUE;
+}
+
+/*----------------------------------------------------------------------------+
+ | Ext_bus_cntlr_init.
+ | Initialize the external bus controller
+ +----------------------------------------------------------------------------*/
+void ext_bus_cntlr_init(void)
+{
+ unsigned long sdr0_pstrp0, sdr0_sdstp1;
+ unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
+ unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
+ unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
+ unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
+ unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
+
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 1 : Initialize EBC Bank 5
+ | ==============================
+ | Bank5 is always associated to the NVRAM/EPLD.
+ | It has to be initialized prior to other banks settings computation since
+ | some board registers values may be needed
+ |
+ +-------------------------------------------------------------------------*/
+ /* NVRAM - FPGA */
+ mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
+ mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 2 : Determine which boot device was selected
+ | =========================================
+ |
+ | Read Pin Strap Register in PPC440EP
+ | In case of boot from IIC, read Serial Device Strap Register1
+ |
+ | Result can either be :
+ | - Boot from EBC 8bits => SMALL FLASH
+ | - Boot from EBC 16bits => Large Flash or SRAM
+ | - Boot from NAND Flash
+ | - Boot from PCI
+ |
+ +-------------------------------------------------------------------------*/
+ /* Read Pin Strap Register in PPC440EP */
+ mfsdr(sdr_pstrp0, sdr0_pstrp0);
+ bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass1
+ +-------------------------------------------------------------------------*/
+ if (is_powerpc440ep_pass1() == TRUE) {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass2
+ +-------------------------------------------------------------------------*/
+ else {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+ /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
+ /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Default Strap Settings 5-7 */
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(sdr_sdstp1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 3 : Compute EBC settings depending on selected boot device
+ | ====== ======================================================
+ |
+ | Resulting EBC init will be among following configurations :
+ |
+ | - Boot from EBC 8bits => boot from SMALL FLASH selected
+ | EBC-CS0 = Small Flash
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Soft Config
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
+ | EBC-CS0 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = Small Flash
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from NAND Flash
+ | EBC-CS0 = NAND Flash0
+ | EBC-CS1,2,3 = NAND Flash1
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from PCI
+ | EBC-CS0 = ...
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM or
+ | Small Flash depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ +-------------------------------------------------------------------------*/
+
+ switch(computed_boot_device) {
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_SMALL_FLASH:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
+ ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_NAND_FLASH0:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = 0;
+ ebc0_cs0_bncr_value = 0;
+
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_PCI:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = 0;
+ ebc0_cs0_bncr_value = 0;
+
+ if ((is_nand_selected()) == TRUE) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+
+ if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+ /* Small Flash */
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+ } else {
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+ }
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_DEVICE_UNKNOWN:
+ /*------------------------------------------------------------------------- */
+ /* Error */
+ break;
+
+ }
+
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
+ EBC0_CFG_PTD_ENABLED |
+ EBC0_CFG_RTC_2048PERCLK |
+ EBC0_CFG_EMPL_LOW |
+ EBC0_CFG_EMPH_LOW |
+ EBC0_CFG_CSTC_DRIVEN |
+ EBC0_CFG_BPF_ONEDW |
+ EBC0_CFG_EMS_8BIT |
+ EBC0_CFG_PME_DISABLED |
+ EBC0_CFG_PMT_ENCODE(0) );
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC Bank 0-4
+ +-------------------------------------------------------------------------*/
+ /* EBC Bank0 */
+ mtebc(pb0ap, ebc0_cs0_bnap_value);
+ mtebc(pb0cr, ebc0_cs0_bncr_value);
+ /* EBC Bank1 */
+ mtebc(pb1ap, ebc0_cs1_bnap_value);
+ mtebc(pb1cr, ebc0_cs1_bncr_value);
+ /* EBC Bank2 */
+ mtebc(pb2ap, ebc0_cs2_bnap_value);
+ mtebc(pb2cr, ebc0_cs2_bncr_value);
+ /* EBC Bank3 */
+ mtebc(pb3ap, ebc0_cs3_bnap_value);
+ mtebc(pb3cr, ebc0_cs3_bncr_value);
+ /* EBC Bank4 */
+ mtebc(pb4ap, ebc0_cs4_bnap_value);
+ mtebc(pb4cr, ebc0_cs4_bncr_value);
+
+ return;
+}
+
+
+/*----------------------------------------------------------------------------+
+ | get_uart_configuration.
+ +----------------------------------------------------------------------------*/
+uart_config_nb_t get_uart_configuration(void)
{
+ return (L4); /* test-only */
+}
+
+/*----------------------------------------------------------------------------+
+ | set_phy_configuration_through_fpga => to EPLD
+ +----------------------------------------------------------------------------*/
+void set_phy_configuration_through_fpga(zmii_config_t config)
+{
+
+ unsigned long fpga_selection_reg;
+
+ fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
+
+ switch(config)
+ {
+ case ZMII_CONFIGURATION_IS_MII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
+ break;
+ case ZMII_CONFIGURATION_IS_RMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
+ break;
+ case ZMII_CONFIGURATION_IS_SMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
+ break;
+ case ZMII_CONFIGURATION_UNKNOWN:
+ default:
+ break;
+ }
+ out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
}
+
+/*----------------------------------------------------------------------------+
+ | scp_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void scp_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | iic1_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void iic1_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_reset_through_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_reset_through_fpga(void)
+{
+ /* Perform soft Reset pulse */
+ unsigned long fpga_reset_reg;
+ int i;
+
+ fpga_reset_reg = in8(FPGA_RESET_REG);
+ out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
+ for (i=0; i<500; i++)
+ udelay(1000);
+ out8(FPGA_RESET_REG,fpga_reset_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_host_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_host_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | ndfc_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void ndfc_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
+ /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
+ /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | uart_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
+{
+ /* FPGA register */
+ unsigned char fpga_selection_3_reg;
+
+ /* Read FPGA Reagister */
+ fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
+
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+ break;
+
+ case L4:
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ for (;;)
+ ;
+ break;
+
+ }
+}
+
+
+/*----------------------------------------------------------------------------+
+ | init_default_gpio
+ +----------------------------------------------------------------------------*/
+void init_default_gpio(void)
+{
+ int i;
+
+ /* Init GPIO0 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO0][i].add = GPIO0_BASE;
+ gpio_tab[GPIO0][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
+ }
+
+ /* Init GPIO1 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO1][i].add = GPIO1_BASE;
+ gpio_tab[GPIO1][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
+ }
+
+ /* EBC_CS_N(5) - GPIO0_10 */
+ gpio_tab[GPIO0][10].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
+
+ /* EBC_CS_N(4) - GPIO0_9 */
+ gpio_tab[GPIO0][9].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uart_ios
+ +------------------------------------------------------------------------------
+ |
+ | Set UART Configuration in PowerPC440EP
+ |
+ | +---------------------------------------------------------------------+
+ | | Configuartion | Connector | Nb of pins | Pins | Associated |
+ | | Number | Port Name | available | naming | CORE |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L1 | Port_A | 8 | UART | UART core 0 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L2 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L3 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
+ | | | Port_C | 2 | UART3 | UART core 2 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | | Port_A | 2 | UART1 | UART core 0 |
+ | | L4 | Port_B | 2 | UART2 | UART core 1 |
+ | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
+ | | | Port_D | 2 | UART4 | UART core 3 |
+ | +-----------------+---------------+------------+--------+-------------+
+ |
+ | Involved GPIOs
+ |
+ | +------------------------------------------------------------------------------+
+ | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
+ | +---------+------------------+-----+-----------------+-----+-------------+-----+
+ | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
+ | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
+ | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
+ | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
+ | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
+ | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
+ | +------------------------------------------------------------------------------+
+ |
+ |
+ +----------------------------------------------------------------------------*/
+
+void update_uart_ios(uart_config_nb_t uart_config)
+{
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L4:
+ /* ----------------------------------------------------------------------- */
+ /* L4 configuration: UART0 = 2 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* UART3 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ printf("ERROR - Unsupported UART configuration number.\n\n");
+ for (;;)
+ ;
+ break;
+
+ }
+
+ /* Set input Selection Register on Alt_Receive for UART Input Core */
+ out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
+ out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
+ out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ndfc_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_ndfc_ios(void)
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
+ gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+
+#if 0
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
#endif
+}
+
+/*----------------------------------------------------------------------------+
+ | update_zii_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_zii_ios(void)
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
+ gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
+ gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
+ gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
+ gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
+ gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
+ gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
+ gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
+ gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
+ gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
+ gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
+ gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
+ gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
+ gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
+ gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_0_3_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(void)
+{
+ gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
+ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
+ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
+ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
+ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_4_9_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_a_b_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_c_d_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(void)
+{
+ gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
+ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
+ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
+ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
+ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
+ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
+ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ebc_master_ios().
+ +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(void)
+{
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_usb2_device_ios().
+ +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(void)
+{
+ gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
+ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
+ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
+ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
+ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_pci_patch_ios().
+ +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(void)
+{
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | set_chip_gpio_configuration(unsigned char gpio_core)
+ | Put the core impacted by clock modification and sharing in reset.
+ | Config the select registers to resolve the sharing depending of the config.
+ | Configure the GPIO registers.
+ |
+ +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core)
+{
+ unsigned char i=0, j=0, reg_offset = 0;
+ unsigned long gpio_reg, gpio_core_add;
+
+ /* GPIO config of the GPIOs 0 to 31 */
+ for (i=0; i<GPIO_MAX; i++, j++)
+ {
+ if (i == GPIO_MAX/2)
+ {
+ reg_offset = 4;
+ j = i-16;
+ }
+
+ gpio_core_add = gpio_tab[gpio_core][i].add;
+
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------+
+ | force_bup_core_selection.
+ +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+ /* Pointer invalid */
+ if (core_select_P == NULL)
+ {
+ printf("Configuration invalid pointer 1\n");
+ for (;;)
+ ;
+ }
+
+ /* L4 Selection */
+ *(core_select_P+UART_CORE0) = CORE_SELECTED;
+ *(core_select_P+UART_CORE1) = CORE_SELECTED;
+ *(core_select_P+UART_CORE2) = CORE_SELECTED;
+ *(core_select_P+UART_CORE3) = CORE_SELECTED;
+
+ /* RMII Selection */
+ *(core_select_P+RMII_SEL) = CORE_SELECTED;
+
+ /* External Interrupt 0-9 selection */
+ *(core_select_P+UIC_0_3) = CORE_SELECTED;
+ *(core_select_P+UIC_4_9) = CORE_SELECTED;
+
+ *(core_select_P+SCP_CORE) = CORE_SELECTED;
+ *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
+ *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
+ *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
+
+ *config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | configure_ppc440ep_pins.
+ +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+ uart_config_nb_t uart_configuration;
+ config_validity_t config_val = CONFIG_IS_INVALID;
+
+ /* Create Core Selection Table */
+ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+ {
+ CORE_NOT_SELECTED, /* IIC_CORE, */
+ CORE_NOT_SELECTED, /* SPC_CORE, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
+ CORE_NOT_SELECTED, /* UIC_4_9, */
+ CORE_NOT_SELECTED, /* USB2_HOST, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
+ CORE_NOT_SELECTED, /* USB2_DEVICE, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
+ CORE_NOT_SELECTED, /* USB1_DEVICE, */
+ CORE_NOT_SELECTED, /* EBC_MASTER, */
+ CORE_NOT_SELECTED, /* NAND_FLASH, */
+ CORE_NOT_SELECTED, /* UART_CORE0, */
+ CORE_NOT_SELECTED, /* UART_CORE1, */
+ CORE_NOT_SELECTED, /* UART_CORE2, */
+ CORE_NOT_SELECTED, /* UART_CORE3, */
+ CORE_NOT_SELECTED, /* MII_SEL, */
+ CORE_NOT_SELECTED, /* RMII_SEL, */
+ CORE_NOT_SELECTED, /* SMII_SEL, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
+ CORE_NOT_SELECTED, /* UIC_0_3 */
+ CORE_NOT_SELECTED, /* USB1_HOST */
+ CORE_NOT_SELECTED /* PCI_PATCH */
+ };
+
+
+ /* Table Default Initialisation + FPGA Access */
+ init_default_gpio();
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* Update Table */
+ force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+ /* If we are running PIBS 1, force known configuration */
+ update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+ /*----------------------------------------------------------------------------+
+ | SDR + ios table update + fpga initialization
+ +----------------------------------------------------------------------------*/
+ unsigned long sdr0_pfc1 = 0;
+ unsigned long sdr0_usb0 = 0;
+ unsigned long sdr0_mfr = 0;
+
+ /* PCI Always selected */
+
+ /* I2C Selection */
+ if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+ iic1_selection_in_fpga();
+ }
+
+ /* SCP Selection */
+ if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+ scp_selection_in_fpga();
+ }
+
+ /* UIC 0:3 Selection */
+ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+ {
+ update_uic_0_3_irq_ios();
+ dma_a_b_unselect_in_fpga();
+ }
+
+ /* UIC 4:9 Selection */
+ if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+ update_uic_4_9_irq_ios();
+ }
+
+ /* DMA AB Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+ update_dma_a_b_ios();
+ dma_a_b_selection_in_fpga();
+ }
+
+ /* DMA CD Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+ {
+ update_dma_c_d_ios();
+ dma_c_d_selection_in_fpga();
+ }
+
+ /* EBC Master Selection */
+ if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_ebc_master_ios();
+ }
+
+ /* PCI Patch Enable */
+ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_pci_patch_ios();
+ }
+
+ /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+ if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+ {
+ /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+ printf("Invalid configuration => USB2 Host selected\n");
+ for (;;)
+ ;
+ /*usb2_host_selection_in_fpga(); */
+ }
+
+ /* USB2.0 Device Selection */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ {
+ update_usb2_device_ios();
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+
+ usb2_device_selection_in_fpga();
+ }
+
+ /* USB1.1 Device Selection */
+ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* USB1.1 Host Selection */
+ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* NAND Flash Selection */
+ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+ {
+ update_ndfc_ios();
+
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ SDR0_CUST0_CHIPSELGAT_EN1 );
+ /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
+ /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
+
+ ndfc_selection_in_fpga();
+ }
+ else
+ {
+ /* Set Mux on EMAC */
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
+ }
+
+ /* MII Selection */
+ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+ }
+
+ /* RMII Selection */
+ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+ }
+
+ /* SMII Selection */
+ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+ }
+
+ /* UART Selection */
+ uart_configuration = get_uart_configuration();
+ switch (uart_configuration)
+ {
+ case L1: /* L1 Selection */
+ /* UART0 8 pins Only */
+ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+ break;
+ case L2: /* L2 Selection */
+ /* UART0 and UART1 4 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L3: /* L3 Selection */
+ /* UART0 4 pins, UART1 and UART2 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L4: /* L4 Selection */
+ /* UART0, UART1, UART2 and UART3 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ }
+ update_uart_ios(uart_configuration);
+
+ /* UART Selection in all cases */
+ uart_selection_in_fpga(uart_configuration);
+
+ /* Packet Reject Function Available */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+ {
+ /* Set UPR Bit in SDR0_PFC1 Register */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+ }
+
+ /* Packet Reject Function Enable */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+ {
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+ mtsdr(sdr_mfr, sdr0_mfr);
+ }
+
+ /* Perform effective access to hardware */
+ mtsdr(sdr_pfc1, sdr0_pfc1);
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* USB2.0 Device Reset must be done after GPIO setting */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ usb2_device_reset_through_fpga();
+
+}
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
new file mode 100644
index 000000000..612e9af7d
--- /dev/null
+++ b/board/amcc/bamboo/bamboo.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*----------------------------------------------------------------------------+
+ | FPGA registers and bit definitions
+ +----------------------------------------------------------------------------*/
+/*
+ * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
+ * TLB initialization makes it correspond to logical address 0x80001FF0.
+ * => Done init_chip.s in bootlib
+ */
+#define FPGA_BASE_ADDR 0x80002000
+
+/*----------------------------------------------------------------------------+
+ | Board Jumpers Setting Register
+ | Board Settings provided by jumpers
+ +----------------------------------------------------------------------------*/
+#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
+/* Boot from small flash */
+#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
+/* Operational Flash versus SRAM position in Memory Map */
+#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
+#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
+#define FPGA_SET_REG_SRAM_ABOVE 0x00
+/* Boot From NAND Flash */
+#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
+#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
+/* On Board PCI Arbiter Select */
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 1
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
+#define FPGA_SEL_1_REG_PHY_MASK 0xE0
+#define FPGA_SEL_1_REG_MII 0x80
+#define FPGA_SEL_1_REG_RMII 0x40
+#define FPGA_SEL_1_REG_SMII 0x20
+#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
+#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
+#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
+#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 2
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
+#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
+#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
+#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
+#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
+#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
+#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
+#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
+ /* 1 = TC - output from 440EP */
+#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
+ /* 1 = TC (output from 440EP) */
+#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 3
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
+#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
+#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
+#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
+#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
+
+/*----------------------------------------------------------------------------+
+ | Soft Reset Register
+ +----------------------------------------------------------------------------*/
+#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
+#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
+#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
+#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
+
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define SDR0_SDSTP0 0x0020
+/* Serial Device Strap Reg 1 */
+#define SDR0_SDSTP1 0x0021
+/* Serial Device Strap Reg 2 */
+#define SDR0_SDSTP2 SDR0_STRP2
+/* Serial Device Strap Reg 3 */
+#define SDR0_SDSTP3 SDR0_STRP3
+
+#define sdr_pstrp0 0x0040
+
+#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
+#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
+
+#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
+#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
+#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
+#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+/*----------------------------------------------------------------------------+
+| EBC Configuration Register - EBC0_CFG
++----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN 0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED 0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK 0x38000000
+#define EBC0_CFG_RTC_16PERCLK 0x00000000
+#define EBC0_CFG_RTC_32PERCLK 0x08000000
+#define EBC0_CFG_RTC_64PERCLK 0x10000000
+#define EBC0_CFG_RTC_128PERCLK 0x18000000
+#define EBC0_CFG_RTC_256PERCLK 0x20000000
+#define EBC0_CFG_RTC_512PERCLK 0x28000000
+#define EBC0_CFG_RTC_1024PERCLK 0x30000000
+#define EBC0_CFG_RTC_2048PERCLK 0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW 0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
+#define EBC0_CFG_EMPL_HIGH 0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW 0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
+#define EBC0_CFG_EMPH_HIGH 0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN 0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW 0x00000000
+#define EBC0_CFG_BPF_TWODW 0x00100000
+#define EBC0_CFG_BPF_FOURDW 0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT 0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED 0x00000000
+#define EBC0_CFG_PME_ENABLED 0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Configuration Register - EBC0_BnCR
++----------------------------------------------------------------------------*/
+/* BAS - Base Address Select */
+#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
+/* BS - Bank Size */
+#define EBC0_BNCR_BS_MASK 0x000E0000
+#define EBC0_BNCR_BS_1MB 0x00000000
+#define EBC0_BNCR_BS_2MB 0x00020000
+#define EBC0_BNCR_BS_4MB 0x00040000
+#define EBC0_BNCR_BS_8MB 0x00060000
+#define EBC0_BNCR_BS_16MB 0x00080000
+#define EBC0_BNCR_BS_32MB 0x000A0000
+#define EBC0_BNCR_BS_64MB 0x000C0000
+#define EBC0_BNCR_BS_128MB 0x000E0000
+/* BU - Bank Usage */
+#define EBC0_BNCR_BU_MASK 0x00018000
+#define EBC0_BNCR_BU_RO 0x00008000
+#define EBC0_BNCR_BU_WO 0x00010000
+#define EBC0_BNCR_BU_RW 0x00018000
+/* BW - Bus Width */
+#define EBC0_BNCR_BW_MASK 0x00006000
+#define EBC0_BNCR_BW_8BIT 0x00000000
+#define EBC0_BNCR_BW_16BIT 0x00002000
+#define EBC0_BNCR_BW_32BIT 0x00004000
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Access Parameters - EBC0_BnAP
++----------------------------------------------------------------------------*/
+/* Burst Mode Enable */
+#define EBC0_BNAP_BME_ENABLED 0x80000000
+#define EBC0_BNAP_BME_DISABLED 0x00000000
+/* Transfert Wait */
+#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
+/* Chip Select On Timing */
+#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
+/* Output Enable On Timing */
+#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
+/* Write Back Enable On Timing */
+#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
+/* Write Back Enable Off Timing */
+#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
+/* Transfert Hold */
+#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
+/* PerReady Enable */
+#define EBC0_BNAP_RE_ENABLED 0x00000100
+#define EBC0_BNAP_RE_DISABLED 0x00000000
+/* Sample On Ready */
+#define EBC0_BNAP_SOR_DELAYED 0x00000000
+#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
+/* Byte Enable Mode */
+#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
+#define EBC0_BNAP_BEM_RW 0x00000040
+/* Parity Enable */
+#define EBC0_BNAP_PEN_DISABLED 0x00000000
+#define EBC0_BNAP_PEN_ENABLED 0x00000020
+
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+/* */
+#define BOOT_FROM_SMALL_FLASH 0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
+#define BOOT_FROM_NAND_FLASH0 0x02
+#define BOOT_FROM_PCI 0x03
+#define BOOT_DEVICE_UNKNOWN 0x04
+
+
+#define PVR_POWERPC_440EP_PASS1 0x42221850
+#define PVR_POWERPC_440EP_PASS2 0x422218D3
+
+#define TRUE 1
+#define FALSE 0
+
+#define GPIO_GROUP_MAX 2
+#define GPIO_MAX 32
+#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
+#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+ /* For the other GPIO number, you must shift */
+
+#define GPIO0 0
+#define GPIO1 1
+
+
+/*#define MAX_SELECTION_NB CORE_NB */
+#define MAX_CORE_SELECT_NB 22
+
+/*----------------------------------------------------------------------------+
+ | PPC440EP GPIOs addresses.
+ +----------------------------------------------------------------------------*/
+#define GPIO0_BASE 0xEF600B00
+#define GPIO0_REAL 0xEF600B00
+
+#define GPIO1_BASE 0xEF600C00
+#define GPIO1_REAL 0xEF600C00
+
+/* Offsets */
+#define GPIOx_OR 0x00 /* GPIO Output Register */
+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
+#define GPIOx_IR 0x1C /* GPIO Input Register */
+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
+
+/* GPIO0 */
+#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
+
+/* GPIO1 */
+#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
+
+
+/*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long add; /* gpio core base address */
+ gpio_driver_t in_out; /* Driver Setting */
+ gpio_select_t alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+/*----------------------------------------------------------------------------+
+ | XX XX
+ |
+ | XXXXXX XXX XX XXX XXX
+ | XX XX X XX XX XX
+ | XX XX X XX XX XX
+ | XX XX XX XX XX
+ | XXXXXX XXX XXX XXXX XXXX
+ +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+ | Defines
+ +----------------------------------------------------------------------------*/
+typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
+ ZMII_CONFIGURATION_IS_MII,
+ ZMII_CONFIGURATION_IS_RMII,
+ ZMII_CONFIGURATION_IS_SMII
+} zmii_config_t;
+
+/*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
+typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
+typedef enum config_list { IIC_CORE,
+ SCP_CORE,
+ DMA_CHANNEL_AB,
+ UIC_4_9,
+ USB2_HOST,
+ DMA_CHANNEL_CD,
+ USB2_DEVICE,
+ PACKET_REJ_FUNC_AVAIL,
+ USB1_DEVICE,
+ EBC_MASTER,
+ NAND_FLASH,
+ UART_CORE0,
+ UART_CORE1,
+ UART_CORE2,
+ UART_CORE3,
+ MII_SEL,
+ RMII_SEL,
+ SMII_SEL,
+ PACKET_REJ_FUNC_EN,
+ UIC_0_3,
+ USB1_HOST,
+ PCI_PATCH,
+ CORE_NB
+} core_list_t;
+
+typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
+ B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
+ B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+ B3_V16, B3_VALUE_UNKNOWN
+} block3_value_t;
+
+typedef enum config_validity { CONFIG_IS_VALID,
+ CONFIG_IS_INVALID
+} config_validity_t;
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 4ab0ea008..35cb65584 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -21,17 +21,7 @@
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0x00001000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
-else
TEXT_BASE = 0xFFF80000
-endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
new file mode 100644
index 000000000..97a4b988d
--- /dev/null
+++ b/board/amcc/bamboo/flash.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "bamboo.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
+ {0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/
+ {0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/
+ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+ unsigned long val;
+ unsigned long ebc_boot_size;
+ unsigned long boot_selection;
+
+ mfsdr(sdr_pstrp0, val);
+ index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
+
+ if ((index == 5) || (index == 7)) {
+ /*
+ * Boot Settings in IIC EEprom address 0xA8 or 0xA4
+ * Read Serial Device Strap Register1 in PPC440EP
+ */
+ mfsdr(sdr_sdstp1, val);
+ boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ index = 3;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ index = 0;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ index = 1;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ index = 2;
+ break;
+ }
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 7ba43c7b0..907029345 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -93,7 +93,7 @@ tlbtab:
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index a4016d540..c978dbafe 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -74,7 +74,7 @@ SECTIONS
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
@@ -150,6 +150,9 @@ SECTIONS
*(.bss)
*(COMMON)
}
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
_end = . ;
PROVIDE (end = .);
}
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index 7311c4edd..3a50b095c 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -41,6 +41,14 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
* Functions
*/
static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
void flash_print_info(flash_info_t * info)
{
@@ -113,6 +121,9 @@ void flash_print_info(flash_info_t * info)
case FLASH_SST160A:
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
default:
printf("Unknown Chip Type\n");
break;
@@ -154,8 +165,22 @@ void flash_print_info(flash_info_t * info)
/*
* The following code cannot be run from FLASH!
*/
+#ifdef CFG_FLASH_2ND_16BIT_DEV
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1) {
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
short i;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
@@ -193,7 +218,6 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
}
value = addr2[1]; /* device ID */
-
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
@@ -323,7 +347,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
return (info->size);
}
-int wait_for_DQ7(flash_info_t * info, int sect)
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile CFG_FLASH_WORD_SIZE *addr =
@@ -346,7 +370,22 @@ int wait_for_DQ7(flash_info_t * info, int sect)
return 0;
}
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
@@ -416,7 +455,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
- wait_for_DQ7(info, sect);
+ wait_for_DQ7_1(info, sect);
}
}
@@ -506,12 +545,334 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
}
/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
+ * Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
{
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
@@ -553,3 +914,4 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
return (0);
}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 9c17e31bd..b60d1221d 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -166,7 +166,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
failsafe--;
if (failsafe == 0)
break;
-
}
/* EMAC RESET */
@@ -223,18 +222,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif
/* MAL RESET */
- mtdcr (malmcr, MAL_CR_MMSR);
- /* wait for reset */
- while (mfdcr (malmcr) & MAL_CR_MMSR) {
- };
+ mtdcr (malmcr, MAL_CR_MMSR);
+ /* wait for reset */
+ while (mfdcr (malmcr) & MAL_CR_MMSR) {
+ };
+
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
out32 (ZMII_FER, 0);
udelay(100);
/* set RII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#elif defined(CONFIG_440)
- /* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
/* MAL Channel RESET */
@@ -324,14 +324,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
-#if defined(CONFIG_440)
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if( get_pvr() == PVR_440GP_RB)
- mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- else
-#else
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
-#endif
+ /* Errata 1.12: MAL_1 -- Disable MAL bursting */
+ if (get_pvr() == PVR_440GP_RB) {
+ mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+ }
/* Free "old" buffers */
if (hw_p->alloc_tx_buf)
@@ -418,6 +415,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
reg |= dev->enetaddr[5];
out32 (EMAC_IAL + hw_p->hw_addr, reg);
+
switch (devnum) {
#if defined(CONFIG_NET_MULTI)
case 1:
@@ -498,7 +496,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif
-
/* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
index 24e6ef357..f4004fb78 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -391,6 +391,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
+#if defined(CONFIG_440_GX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@@ -405,7 +406,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-
+#endif /* defined(CONFIG_440_GX) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
@@ -432,6 +433,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
bis->bi_phynum[devnum] = reg;
+#ifndef CONFIG_NO_PHY_RESET
/*
* Reset the phy, only if its the first time through
* otherwise, just check the speeds & feeds
@@ -441,35 +443,36 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_CIS8201_PHY)
- /*
- * Cicada 8201 PHY needs to have an extended register whacked
- * for RGMII mode.
- */
- if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
- miiphy_write (reg, 23, 0x1200);
/*
- * Vitesse VSC8201/Cicada CIS8201 errata:
- * Interoperability problem with Intel 82547EI phys
- * This work around (provided by Vitesse) changes
- * the default timer convergence from 8ms to 12ms
+ * Cicada 8201 PHY needs to have an extended register whacked
+ * for RGMII mode.
*/
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0200);
- miiphy_write (reg, 0x1f, 0x52b5);
- miiphy_write (reg, 0x02, 0x0004);
- miiphy_write (reg, 0x01, 0x0671);
- miiphy_write (reg, 0x00, 0x8fae);
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0000);
- miiphy_write (reg, 0x1f, 0x0000);
- /* end Vitesse/Cicada errata */
- }
+ if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
+ miiphy_write (reg, 23, 0x1200);
+ /*
+ * Vitesse VSC8201/Cicada CIS8201 errata:
+ * Interoperability problem with Intel 82547EI phys
+ * This work around (provided by Vitesse) changes
+ * the default timer convergence from 8ms to 12ms
+ */
+ miiphy_write (reg, 0x1f, 0x2a30);
+ miiphy_write (reg, 0x08, 0x0200);
+ miiphy_write (reg, 0x1f, 0x52b5);
+ miiphy_write (reg, 0x02, 0x0004);
+ miiphy_write (reg, 0x01, 0x0671);
+ miiphy_write (reg, 0x00, 0x8fae);
+ miiphy_write (reg, 0x1f, 0x2a30);
+ miiphy_write (reg, 0x08, 0x0000);
+ miiphy_write (reg, 0x1f, 0x0000);
+ /* end Vitesse/Cicada errata */
+ }
#endif
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (reg);
udelay (1000);
}
+#endif /* CONFIG_NO_PHY_RESET */
miiphy_read (reg, PHY_BMSR, &reg_short);
@@ -538,14 +541,16 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* set the Mal configuration reg */
+#if defined(CONFIG_440_GX)
+ mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+ MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+#else
+ mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr () == PVR_440GP_RB)
- mtdcr (malmcr,
- MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- else
- mtdcr (malmcr,
- MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
- MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+ if (get_pvr() == PVR_440GP_RB) {
+ mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
+ }
+#endif
/* Free "old" buffers */
if (hw_p->alloc_tx_buf)
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index ae45a23d0..3a4b5d016 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -152,7 +152,7 @@ int checkcpu (void)
#endif
#if defined(CONFIG_440)
- puts ("AMCC PowerPC 440 ");
+ puts ("AMCC PowerPC 440");
switch(pvr) {
case PVR_440GP_RB:
puts("GP Rev. B");
@@ -195,7 +195,7 @@ int checkcpu (void)
#endif
default:
- printf ("UNKNOWN (PVR=%08x)", pvr);
+ printf (" UNKNOWN (PVR=%08x)", pvr);
break;
}
#endif
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 520107a8f..e2eab629f 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1590,7 +1590,6 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long dimm_num;
- unsigned long bxcr_num;
unsigned long bank_base_addr;
unsigned long bank_size_bytes;
unsigned long cr;
@@ -1601,6 +1600,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
unsigned char num_banks;
unsigned char bank_size_id;
+#ifndef CONFIG_BAMBOO
+ unsigned long bxcr_num;
/*
* Set the BxCR regs. First, wipe out the bank config registers.
@@ -1609,11 +1610,16 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
mtdcr(memcfgd, 0x00000000);
}
+#endif
/*
* reset the bank_base address
*/
+#ifndef CONFIG_BAMBOO
bank_base_addr = CFG_SDRAM_BASE;
+#else
+ bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
+#endif
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
@@ -1691,7 +1697,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
+-----------------------------------------------------------------*/
if (dimm_num == 0) {
for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
mtdcr(memcfga, mem_b0cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b1cr + (i << 2));
+#endif
temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK |
@@ -1703,7 +1713,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
}
} else {
for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
mtdcr(memcfga, mem_b2cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b3cr + (i << 2));
+#endif
temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK |
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 3a8ff2b02..788c71cc2 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -379,11 +379,13 @@ __440gx_msr_continue:
li r0,0
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
/* Clear Dcache to use as RAM */
- lis r3,CFG_INIT_RAM_ADDR@h
- li r4,CFG_INIT_RAM_END@l
+ addis r3,r0,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ addis r4,r0,CFG_INIT_RAM_END@h
+ ori r4,r4,CFG_INIT_RAM_END@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
- beq ..d_ran
+ beq ..d_ran
addi r5,r5,0x0001
..d_ran:
mtctr r5
diff --git a/include/440gx_enet.h b/include/440gx_enet.h
index 022c5d871..190b454cb 100644
--- a/include/440gx_enet.h
+++ b/include/440gx_enet.h
@@ -318,6 +318,8 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M0_RXE (0x08000000)
#define EMAC_M0_WKE (0x04000000)
+/* on 440GX EMAC_MR1 has a different layout! */
+#if defined(CONFIG_440_GX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@@ -347,6 +349,31 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M1_OBCI_83 (0x00000010)
#define EMAC_M1_OBCI_66 (0x00000008)
#define EMAC_M1_RSVD1 (0x00000007)
+#else /* defined(CONFIG_440_GX) */
+/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
+#define EMAC_M1_FDE 0x80000000
+#define EMAC_M1_ILE 0x40000000
+#define EMAC_M1_VLE 0x20000000
+#define EMAC_M1_EIFC 0x10000000
+#define EMAC_M1_APP 0x08000000
+#define EMAC_M1_AEMI 0x02000000
+#define EMAC_M1_IST 0x01000000
+#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS 0x00400000
+#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K 0x00200000
+#define EMAC_M1_RFS_1K 0x00100000
+#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_1K 0x00040000
+#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
+#define EMAC_M1_TR0_MULTI 0x00008000
+#define EMAC_M1_TR1_DEPEND 0x00004000
+#define EMAC_M1_TR1_MULTI 0x00002000
+#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
+#define EMAC_M1_JUMBO_ENABLE 0x00001000
+#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
+#endif /* defined(CONFIG_440_GX) */
+
/* Transmit Mode Register 0 */
#define EMAC_TXM0_GNP0 (0x80000000)
#define EMAC_TXM0_GNP1 (0x40000000)
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 6ccd8b9f3..bb5685a66 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -30,59 +30,52 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
-#define CONFIG_440_EP 1 /* Specific PPC440EP support */
+#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
+#define CONFIG_440_EP 1 /* Specific PPC440EP support */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#undef CFG_DRAM_TEST /* disable - takes long time! */
-/*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
-
+#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
-#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
-#define CFG_USB_DEVICE 0x50000000
-#define CFG_NVRAM_BASE_ADDR 0x80000000
-#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
-#define CFG_INIT_RAM_END 0x2000
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
-/*#define CFG_SDRAM_BANKS (2) */
-#define CFG_SDRAM_BANKS (1)
-
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
-/*define this if you want console on UART1*/
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
@@ -95,37 +88,57 @@
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#if 0 /* test-only */
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
-#else
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2aa
+#define CFG_FLASH_WORD_SIZE unsigned char
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+#if 0 /* test-only */
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
+#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
- *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
+ *----------------------------------------------------------------------------- */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
+#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
/*-----------------------------------------------------------------------
* I2C
@@ -135,44 +148,71 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#define CFG_ENV_IS_IN_EEPROM 1
-
-/* Define to allow the user to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
#define CFG_I2C_MULTI_EEPROMS
-#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
-#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
-#define CONFIG_BOOTDELAY 3 /* disable autoboot */
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=bamboo\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/bamboo/uImage\0" \
+ "kernel_addr=fff00000\0" \
+ "ramdisk_addr=fff10000\0" \
+ "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
+ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
+ "cp.b 100000 fff80000 80000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1 /* required for netconsole */
-#define CONFIG_PHY1_ADDR 3
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.4.251
-#define CONFIG_ETHADDR 00:10:EC:00:12:34
-#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
+#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP 10.0.4.115
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
/* Partitions */
#define CONFIG_MAC_PARTITION
@@ -188,59 +228,23 @@
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG /* watchdog */
-#endif
-
-#ifdef CONFIG_440_EP
- /* Need to define POST */
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- /* CFG_CMD_EXT2 |*/ \
- /* CFG_CMD_FAT |*/ \
- CFG_CMD_I2C | \
- /* CFG_CMD_IDE |*/ \
- CFG_CMD_IRQ | \
- /* CFG_CMD_KGDB |*/ \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_FLASH | \
- /* CFG_CMD_SPI |*/ \
- CFG_CMD_USB | \
- 0 ) & ~CFG_CMD_IMLS)
-#else
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ECHO | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- /* CFG_CMD_EXT2 |*/ \
- /* CFG_CMD_FAT |*/ \
- CFG_CMD_I2C | \
- /* CFG_CMD_IDE |*/ \
- CFG_CMD_IRQ | \
- /* CFG_CMD_KGDB |*/ \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CFG_CMD_FLASH | \
- /* CFG_CMD_SPI |*/ \
- 0 ) & ~CFG_CMD_IMLS)
-#endif
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_USB | \
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -263,8 +267,8 @@
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI 1 /* support kdi files */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
@@ -273,18 +277,18 @@
*-----------------------------------------------------------------------
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
@@ -292,10 +296,11 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
diff --git a/include/ppc440.h b/include/ppc440.h
index 3e9034f35..874fe3433 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -331,6 +331,158 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+
+/* USB Control Register */
+#define SDR0_USB0 0x0320
+#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
+#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
+#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
+#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
+#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0 0x4000
+#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+
+#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+
+#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
+
+/* CUST1 Customer Configuration Register1 */
+#define SDR0_CUST1 0x4002
+#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
+#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+
+/* Pin Function Control Register 0 */
+#define SDR0_PFC0 0x4100
+#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
+#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
+#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
+#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
+#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR 0x4300
+#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+
#else
/*-----------------------------------------------------------------------------