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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-10-07 09:24:10 +0000
committerTom Rini <trini@ti.com>2012-10-08 11:15:04 -0700
commitdec96689caac25780174b4899032faf788824ac4 (patch)
tree49b415b3a1da052b6b3d7fcbf146364991a28fc4
parent8cc64bafc00415877ed51769ca90cb562ded5c01 (diff)
downloadu-boot-linaro-stable-dec96689caac25780174b4899032faf788824ac4.tar.gz
arm: armv7: omap3: Fix restore sequence in lowlevel_init
The restore sequence in lowlevel_init was in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that of s_init, so move the s_init call after the restore and turn it into a tail-optimized branch. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S9
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index ebf69fa17..eacfef8bb 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -214,7 +214,7 @@ pll_div_val5:
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
+ str ip, [sp] /* stash ip register */
mov ip, lr /* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
@@ -224,12 +224,11 @@ ENTRY(lowlevel_init)
ldr r1, =SRAM_CLK_CODE
bl cpy_clk_code
#endif /* NAND Boot */
- bl s_init /* go setup pll, mux, memory */
- ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
+ ldr ip, [sp] /* restore save ip */
+ /* tail-call s_init to setup pll, mux, memory */
+ b s_init
- /* back to arch calling code */
- mov pc, lr
ENDPROC(lowlevel_init)
/* the literal pools origin */