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authorEd Swarthout <Ed.Swarthout@freescale.com>2009-02-24 02:37:59 -0600
committerAndy Fleming <afleming@freescale.com>2009-03-09 17:46:09 -0500
commit0ee84b88b78bce425190d8cd7adf4c30cba0c2f0 (patch)
treef1d7d76e4cf6c382bb00d4d7f1c3a845908b4b7d
parent014c595f12d4f7e14cb10188f856465b2d41718f (diff)
downloadu-boot-linaro-stable-0ee84b88b78bce425190d8cd7adf4c30cba0c2f0.tar.gz
Fix mpc85xx ddr-gen3 ddr_sdram_cfg.
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
-rw-r--r--cpu/mpc85xx/ddr-gen3.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8dc2b3ac5..99c325a4f 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
- /* Do not enable the memory */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
/*