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authorKumar Gala <galak@kernel.crashing.org>2008-10-16 21:58:50 -0500
committerWolfgang Denk <wd@denx.de>2008-10-17 10:51:35 +0200
commitf7d190b1c0b3ab7fc53074ad2862f7de99de37ff (patch)
tree522784dc12eeb2294ddc7b647889691764a3603d
parent42653b826adb319a1df06e24ef26096b2a5d9d2a (diff)
downloadu-boot-linaro-stable-f7d190b1c0b3ab7fc53074ad2862f7de99de37ff.tar.gz
85xx: Using proper I2C source clock divider for MPC8544
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being bit 26, instead it should be bit 28. This caused in incorrect interpretation of the i2c_clk which is the same as the SEC clk on MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported in PORDEVSR2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--include/asm-ppc/immap_85xx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 50c9ddefd..6c81c3996 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1579,7 +1579,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
+#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
char res1[8];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
char res2[12];