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authorSteve Sakoman <steve@sakoman.com>2012-03-02 14:20:31 -0800
committerJohn Rigby <john.rigby@linaro.org>2012-04-25 07:54:11 -0600
commit401339b5f8ba1c0b28a4a5492d3083af90eaa240 (patch)
tree2535cb66fbcd7f462eb5e6c0f81af4d070d0e9a5
parent4c8358d3a155cd5b4f2d765bc5f3464e1380759d (diff)
downloadu-boot-linaro-stable-401339b5f8ba1c0b28a4a5492d3083af90eaa240.tar.gz
overo: support 200Mhz memory on 37XX2012.04.2Linaro-u-boot-2012.04.2
Signed-off-by: Steve Sakoman <steve@sakoman.com>
-rw-r--r--board/overo/overo.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 7b4064cdb..28c7344f0 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -169,16 +169,30 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = MICRON_V_MCFG_165(256 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ if (get_cpu_family() != CPU_OMAP36XX) {
+ *mcfg = MICRON_V_MCFG_165(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_165;
+ *ctrlb = MICRON_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = HYNIX_V_MCFG_165(256 << 20);
- *ctrla = HYNIX_V_ACTIMA_165;
- *ctrlb = HYNIX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ if (get_cpu_family() != CPU_OMAP36XX) {
+ *mcfg = HYNIX_V_MCFG_165(256 << 20);
+ *ctrla = HYNIX_V_ACTIMA_165;
+ *ctrlb = HYNIX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ *mcfg = HYNIX_V_MCFG_200(256 << 20);
+ *ctrla = HYNIX_V_ACTIMA_200;
+ *ctrlb = HYNIX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
break;
default:
*mcfg = MICRON_V_MCFG_165(128 << 20);