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authorwdenk <wdenk>2004-09-28 19:00:19 +0000
committerwdenk <wdenk>2004-09-28 19:00:19 +0000
commitcce625e557416d06aeddaab0967b3119748cd21e (patch)
treef401a0729c8fab8c58cd3b2f55b6205e1d6e77bc
parent66ca92a5ba882807ba8ed8f772c0fc22b25976cc (diff)
downloadu-boot-linaro-stable-cce625e557416d06aeddaab0967b3119748cd21e.tar.gz
* Patch by Stephen Williams, 15 July 2004
Set the PCI class code for JSE board as part of PCI interface setup * Patch by Michael Bendzick, 15 Jul 2004: Fix problem with writes with odd sizes in drivers/cfi_flash.c when CFG_FLASH_USE_BUFFER_WRITE is set
-rw-r--r--CHANGELOG7
-rw-r--r--board/jse/host_bridge.c7
-rw-r--r--drivers/cfi_flash.c3
-rw-r--r--include/configs/NC650.h4
4 files changed, 16 insertions, 5 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 073bfbb72..6c82aa480 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,13 @@
Changes since U-Boot 1.1.1:
======================================================================
+* Patch by Stephen Williams, 15 July 2004
+ Set the PCI class code for JSE board as part of PCI interface setup
+
+* Patch by Michael Bendzick, 15 Jul 2004:
+ Fix problem with writes with odd sizes in drivers/cfi_flash.c when
+ CFG_FLASH_USE_BUFFER_WRITE is set
+
* Patch by Yuli Barcohen, 13 Jul 2004:
Allow clock setting on MPC866/MPC885 series chips according to
environment variable `cpuclk'
diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c
index d68744518..11c41bdad 100644
--- a/board/jse/host_bridge.c
+++ b/board/jse/host_bridge.c
@@ -40,9 +40,12 @@ void host_bridge_init (void)
pci_dev_t dev = PCI_BDF (0, 10, 0);
int rc;
- u32 val32;
- rc = pci_read_config_dword (dev, 0, &val32);
+ /* Set PCI Class code --
+ The primary side sees this class code at 0x08 in the
+ primary config space. This must be something other then a
+ bridge, or MS Windows starts doing weird stuff to me. */
+ pci_write_config_dword (dev, 0x48, 0x04800000);
/* Set subsystem ID --
The primary side sees this value at 0x2c. We set it here so
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index e89f975ce..cd22d60da 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -517,6 +517,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
i = buffered_size > cnt ? cnt : buffered_size;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
+ i -= (i % info->portwidth);
wp += i;
src += i;
cnt -= i;
@@ -1231,5 +1232,5 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 30d3d212e..48bea694d 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -44,7 +44,7 @@
/*
* 10 MHz - PLL input clock
*/
-#define CFG_8xx_OSCCLK 10000000
+#define CONFIG_8xx_OSCLK 10000000
/*
* 50 MHz - default CPU clock
@@ -62,7 +62,7 @@
#define CFG_8xx_CPUCLK_MAX 133000000
#define CFG_MEASURE_CPUCLK
-#define CFG_8XX_XIN CFG_8xx_OSCCLK
+#define CFG_8XX_XIN CONFIG_8xx_OSCLK
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */