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authorstroese <stroese>2003-12-09 14:59:11 +0000
committerstroese <stroese>2003-12-09 14:59:11 +0000
commite075fbe66c6b0d3d8809db5847625fb85864eb48 (patch)
treebef6b200c62f0ee275074412ea40c720d4cf061f
parentabcac8725f77881aa7076b892741b1675df1a65a (diff)
downloadu-boot-linaro-stable-e075fbe66c6b0d3d8809db5847625fb85864eb48.tar.gz
Updated for PPC405EP boards.
-rw-r--r--common/cmd_reginfo.c76
-rw-r--r--include/ppc405.h8
2 files changed, 79 insertions, 5 deletions
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 60a015c2e..edc572801 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -25,7 +25,7 @@
#include <command.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
-#elif defined (CONFIG_405GP)
+#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
#include <asm/processor.h>
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
@@ -89,8 +89,8 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/
/* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */
-#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
- printf("\n405GP registers; MSR=%x\n",mfmsr());
+#elif defined (CONFIG_405GP)
+ printf("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n"
@@ -151,7 +151,7 @@ mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
printf ("\n"
-"pb0cr pb0ap pb1cr bp1ap pb2cr pb2ap pb3cr pb3ap\n");
+"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
@@ -173,6 +173,72 @@ mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
printf ("\n\n");
+/* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
+#elif defined(CONFIG_405EP)
+ printf("\n405EP registers; MSR=%08x\n",mfmsr());
+ printf ("\nUniversal Interrupt Controller Regs\n"
+"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
+"\n"
+"%08x %08x %08x %08x %08x %08x %08x %08x\n",
+ mfdcr(uicsr),
+ mfdcr(uicer),
+ mfdcr(uiccr),
+ mfdcr(uicpr),
+ mfdcr(uictr),
+ mfdcr(uicmsr),
+ mfdcr(uicvr),
+ mfdcr(uicvcr));
+
+ printf ("\nMemory (SDRAM) Configuration\n"
+"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
+
+ mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
+ mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
+ mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
+ mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
+ mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
+ mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
+
+ printf ("\n\n"
+"DMA Channels\n"
+"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
+"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
+"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
+mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
+mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
+mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
+
+ printf (
+"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
+"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
+mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
+mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
+
+ printf ("\n"
+"External Bus\n"
+"pbear pbesr0 pbesr1 epcr\n");
+ mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
+
+ printf ("\n"
+"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
+ mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
+
+ printf ("\n"
+"pb4cr pb4ap\n");
+ mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
+ mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
+
+ printf ("\n\n");
#elif defined(CONFIG_5xx)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
@@ -216,7 +282,7 @@ mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
/**************************************************/
-#if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
+#if (defined(CONFIG_8xx) || defined(CONFIG_405GP) || defined(CONFIG_405EP)) && \
(CONFIG_COMMANDS & CFG_CMD_REGINFO)
U_BOOT_CMD(
diff --git a/include/ppc405.h b/include/ppc405.h
index a0dbbc3d9..29e6ffd0d 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -163,14 +163,17 @@
#define mem_pmit 0x34 /* power management idle timer */
#define mem_mb0cf 0x40 /* memory bank 0 configuration */
#define mem_mb1cf 0x44 /* memory bank 1 configuration */
+#ifndef CONFIG_405EP
#define mem_mb2cf 0x48 /* memory bank 2 configuration */
#define mem_mb3cf 0x4c /* memory bank 3 configuration */
+#endif
#define mem_sdtr1 0x80 /* timing reg 1 */
#ifndef CONFIG_405EP
#define mem_ecccf 0x94 /* ECC configuration */
#define mem_eccerr 0x98 /* ECC error status */
#endif
+#ifndef CONFIG_405EP
/******************************************************************************
* Decompression Controller
******************************************************************************/
@@ -194,6 +197,7 @@
/* There are 0x400 of the following registers, from krom0 to krom3ff*/
/* Only the first one is given here. */
#define krom0 0x400 /* SRAM/ROM read/write */
+#endif
/******************************************************************************
* Power Management
@@ -215,17 +219,21 @@
#define pb2cr 0x02 /* periph bank 2 config reg */
#define pb3cr 0x03 /* periph bank 3 config reg */
#define pb4cr 0x04 /* periph bank 4 config reg */
+#ifndef CONFIG_405EP
#define pb5cr 0x05 /* periph bank 5 config reg */
#define pb6cr 0x06 /* periph bank 6 config reg */
#define pb7cr 0x07 /* periph bank 7 config reg */
+#endif
#define pb0ap 0x10 /* periph bank 0 access parameters */
#define pb1ap 0x11 /* periph bank 1 access parameters */
#define pb2ap 0x12 /* periph bank 2 access parameters */
#define pb3ap 0x13 /* periph bank 3 access parameters */
#define pb4ap 0x14 /* periph bank 4 access parameters */
+#ifndef CONFIG_405EP
#define pb5ap 0x15 /* periph bank 5 access parameters */
#define pb6ap 0x16 /* periph bank 6 access parameters */
#define pb7ap 0x17 /* periph bank 7 access parameters */
+#endif
#define pbear 0x20 /* periph bus error addr reg */
#define pbesr0 0x21 /* periph bus error status reg 0 */
#define pbesr1 0x22 /* periph bus error status reg 1 */