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authorwdenk <wdenk>2004-01-04 22:51:12 +0000
committerwdenk <wdenk>2004-01-04 22:51:12 +0000
commita522fa0e7cdddf8204ba43b335f68be6a42159a5 (patch)
tree3ddc0bffbaade1b79b1ff520ad6051b5a9766278
parent180d3f74e4738ee107e269cbb949481075dd789a (diff)
downloadu-boot-linaro-stable-a522fa0e7cdddf8204ba43b335f68be6a42159a5.tar.gz
* Make BMS2003 use a separate config file to avoid #ifdef mess;
add I2C support; add support for DS1337 RTC * Add CompactFlash support for BMS2003 board * Add support for status LED on BMS2003 board
-rw-r--r--CHANGELOG7
-rw-r--r--Makefile5
-rw-r--r--board/dbau1x00/dbau1x00.c7
-rw-r--r--common/cmd_ide.c85
-rw-r--r--common/cmd_pcmcia.c68
-rw-r--r--include/asm-mips/au1x00.h3
-rw-r--r--include/ata.h2
-rw-r--r--include/configs/TQM823L.h8
-rw-r--r--include/configs/bms2003.h515
-rw-r--r--include/status_led.h17
10 files changed, 698 insertions, 19 deletions
diff --git a/CHANGELOG b/CHANGELOG
index ef42071a3..064bf867b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,13 @@
Changes since U-Boot 1.0.0:
======================================================================
+* Make BMS2003 use a separate config file to avoid #ifdef mess;
+ add I2C support; add support for DS1337 RTC
+
+* Add CompactFlash support for BMS2003 board
+
+* Add support for status LED on BMS2003 board
+
* Patch by Scott McNutt, 02 Jan 2004:
Add support for the Nios Active Serial Memory Interface (ASMI)
on Cyclone devices
diff --git a/Makefile b/Makefile
index 126c9e9d9..706216300 100644
--- a/Makefile
+++ b/Makefile
@@ -261,10 +261,7 @@ AMX860_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
bms2003_config : unconfig
- @echo "#define CONFIG_BMS2003" >include/config.h
- @echo "#define CONFIG_LCD" >>include/config.h
- @echo "#define CONFIG_NEC_NL6448BC33_54" >>include/config.h
- @./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+ @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
c2mon_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx c2mon
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index 8fcbd812a..315e41260 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -39,13 +39,6 @@ long int initdram(int board_type)
/* In cpu/mips/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-#ifdef CONFIG_DBAU1100
-#warning "FIXME Check that bcsr is the same as dbau1000 board!"
-#endif
-#ifdef CONFIG_DBAU1500
-#warning "FIXME Check that bcsr is the same as dbau1000 board!"
-#endif
-
int checkboard (void)
{
u16 status;
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 331041c16..668d838af 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -835,6 +835,7 @@ output_data_short(int dev, ulong *sect_buf, int words)
static void
input_swap_data(int dev, ulong *sect_buf, int words)
{
+#ifndef CONFIG_BMS2003
volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
ushort *dbuf = (ushort *)sect_buf;
@@ -842,6 +843,20 @@ input_swap_data(int dev, ulong *sect_buf, int words)
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
}
+#else /* CONFIG_BMS2003 */
+ uchar i;
+ volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
+ volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
+ ushort *dbuf = (ushort *)sect_buf;
+
+ while (words--) {
+ for (i=0; i<2; i++) {
+ *(((uchar *)(dbuf)) + 1) = *pbuf_even;
+ *(uchar *)dbuf = *pbuf_odd;
+ dbuf+=1;
+ }
+ }
+#endif /* CONFIG_BMS2003 */
}
#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
@@ -850,6 +865,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
static void
output_data(int dev, ulong *sect_buf, int words)
{
+#ifndef CONFIG_BMS2003
ushort *dbuf;
volatile ushort *pbuf;
@@ -861,6 +877,25 @@ output_data(int dev, ulong *sect_buf, int words)
__asm__ volatile ("eieio");
*pbuf = *dbuf++;
}
+#else /* CONFIG_BMS2003 */
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
+ pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
+ dbuf = (uchar *)sect_buf;
+ while (words--) {
+ __asm__ volatile ("eieio");
+ *pbuf_even = *dbuf++;
+ __asm__ volatile ("eieio");
+ *pbuf_odd = *dbuf++;
+ __asm__ volatile ("eieio");
+ *pbuf_even = *dbuf++;
+ __asm__ volatile ("eieio");
+ *pbuf_odd = *dbuf++;
+ }
+#endif /* CONFIG_BMS2003 */
}
#else /* ! __PPC__ */
static void
@@ -874,6 +909,7 @@ output_data(int dev, ulong *sect_buf, int words)
static void
input_data(int dev, ulong *sect_buf, int words)
{
+#ifndef CONFIG_BMS2003
ushort *dbuf;
volatile ushort *pbuf;
@@ -885,6 +921,25 @@ input_data(int dev, ulong *sect_buf, int words)
__asm__ volatile ("eieio");
*dbuf++ = *pbuf;
}
+#else /* CONFIG_BMS2003 */
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
+ pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
+ dbuf = (uchar *)sect_buf;
+ while (words--) {
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_even;
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_odd;
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_even;
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_odd;
+ }
+#endif /* CONFIG_BMS2003 */
}
#else /* ! __PPC__ */
static void
@@ -1409,6 +1464,7 @@ static void ide_led (uchar led, uchar status)
static void
output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
+#ifndef CONFIG_BMS2003
ushort *dbuf;
volatile ushort *pbuf;
@@ -1418,11 +1474,26 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts)
__asm__ volatile ("eieio");
*pbuf = *dbuf++;
}
+#else /* CONFIG_BMS2003 */
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
+ pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
+ while (shorts--) {
+ __asm__ volatile ("eieio");
+ *pbuf_even = *dbuf++;
+ __asm__ volatile ("eieio");
+ *pbuf_odd = *dbuf++;
+ }
+#endif /* CONFIG_BMS2003 */
}
static void
input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
+#ifndef CONFIG_BMS2003
ushort *dbuf;
volatile ushort *pbuf;
@@ -1432,6 +1503,20 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
__asm__ volatile ("eieio");
*dbuf++ = *pbuf;
}
+#else /* CONFIG_BMS2003 */
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
+ pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
+ while (shorts--) {
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_even;
+ __asm__ volatile ("eieio");
+ *dbuf++ = *pbuf_odd;
+ }
+#endif /* CONFIG_BMS2003 */
}
#else /* ! __PPC__ */
diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c
index 1bd4bc532..8c17859da 100644
--- a/common/cmd_pcmcia.c
+++ b/common/cmd_pcmcia.c
@@ -229,7 +229,7 @@ int pcmcia_on (void)
#endif /* CONFIG_IDE_8xx_PCCARD */
#ifdef CONFIG_BMS2003
case 3: { /* map I/O window for 4xUART data/ctrl */
- win->br += 0x140000;
+ win->br += 0x40000;
win->or = ( PCMCIA_BSIZE_256K
| PCMCIA_PPS_8
| PCMCIA_PRS_IO
@@ -622,6 +622,7 @@ static int hardware_enable(int slot)
PCMCIA_PGCRX(slot) = reg;
udelay(500);
+#ifndef CONFIG_BMS2003
#ifndef CONFIG_NSCU
/*
* Configure Port C pins for
@@ -633,6 +634,16 @@ static int hardware_enable(int slot)
immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
#endif
+#else /* CONFIG_BMS2003 */
+ /*
+ * Configure Port B pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_cpm.cp_pbpar &= ~(0x00000300);
+
+ /* remove all power */
+ immap->im_cpm.cp_pbdat |= 0x00000300;
+#endif /* CONFIG_BMS2003 */
/*
* Make sure there is a card in the slot, then configure the interface.
@@ -641,7 +652,11 @@ static int hardware_enable(int slot)
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+#ifndef CONFIG_BMS2003
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+#else
+ if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
+#endif /* CONFIG_BMS2003 */
printf (" No Card found\n");
return (1);
}
@@ -657,14 +672,26 @@ static int hardware_enable(int slot)
(reg&PCMCIA_VS2(slot))?"n":"ff");
#ifndef CONFIG_NSCU
if ((reg & mask) == mask) {
+#ifndef CONFIG_BMS2003
immap->im_ioport.iop_pcdat |= 0x0004;
+#else
+ immap->im_cpm.cp_pbdat &= ~(0x0000100);
+#endif /* CONFIG_BMS2003 */
puts (" 5.0V card found: ");
} else {
+#ifndef CONFIG_BMS2003
immap->im_ioport.iop_pcdat |= 0x0002;
+#else
+ immap->im_cpm.cp_pbdat &= ~(0x0000200);
+#endif /* CONFIG_BMS2003 */
puts (" 3.3V card found: ");
}
+#ifndef CONFIG_BMS2003
immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
#else
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+#endif /* CONFIG_BMS2003 */
+#else
if ((reg & mask) == mask) {
puts (" 5.0V card found: ");
} else {
@@ -708,10 +735,14 @@ static int hardware_disable(int slot)
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+#ifndef CONFIG_BMS2003
#ifndef CONFIG_NSCU
/* remove all power */
immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
#endif
+#else /* CONFIG_BMS2003 */
+ immap->im_cpm.cp_pbdat |= 0x00000300;
+#endif /* CONFIG_BMS2003 */
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
@@ -761,6 +792,7 @@ static int voltage_set(int slot, int vcc, int vpp)
PCMCIA_PGCRX(slot) = reg;
udelay(500);
+#ifndef CONFIG_BMS2003
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable,
@@ -778,6 +810,26 @@ static int voltage_set(int slot, int vcc, int vpp)
case 50: reg |= 0x0004; break;
default: goto done;
}
+#else /* CONFIG_BMS2003 */
+ /*
+ * Configure Port B pins for
+ * 5 Volts Enable and 3 Volts enable,
+ * Turn off all power
+ */
+ debug ("PCMCIA power OFF\n");
+ immap->im_cpm.cp_pbpar &= ~(0x00000300);
+ /* remove all power */
+
+ immap->im_cpm.cp_pbdat |= 0x00000300;
+
+ reg = 0;
+ switch(vcc) {
+ case 0: break;
+ case 33: reg |= 0x00000200; break;
+ case 50: reg |= 0x00000100; break;
+ default: goto done;
+}
+#endif /* CONFIG_BMS2003 */
/* Checking supported voltages */
@@ -785,11 +837,21 @@ static int voltage_set(int slot, int vcc, int vpp)
pcmp->pcmc_pipr,
(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+#ifndef CONFIG_BMS2003
immap->im_ioport.iop_pcdat |= reg;
immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+#else
+ immap->im_cpm.cp_pbdat &= !reg;
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+#endif /* CONFIG_BMS2003 */
if (reg) {
+#ifndef CONFIG_BMS2003
debug ("PCMCIA powered at %sV\n",
(reg&0x0004) ? "5.0" : "3.3");
+#else
+ debug ("PCMCIA powered at %sV\n",
+ (reg&0x00000200) ? "5.0" : "3.3");
+#endif /* CONFIG_BMS2003 */
} else {
debug ("PCMCIA powered down\n");
}
@@ -1774,7 +1836,11 @@ static int hardware_enable (int slot)
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+#ifndef CONFIG_BMS2003
if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+#else
+ if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
+#endif /* CONFIG_BMS2003 */
printf (" No Card found\n");
return (1);
}
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 917fd83ae..317e6daae 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -128,6 +128,9 @@ static __inline__ int au_ffs(int x)
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#endif
+#define CP0_IWATCHLO $18,1
+#define CP0_DEBUG $23
+
/* SDRAM Controller */
#define MEM_SDMODE0 0xB4000000
#define MEM_SDMODE1 0xB4000004
diff --git a/include/ata.h b/include/ata.h
index fa30ee8bd..719f76a2f 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -56,6 +56,8 @@
#define ATA_CYL_HIGH ATA_IO_REG(5)
#define ATA_DEV_HD ATA_IO_REG(6)
#define ATA_COMMAND ATA_IO_REG(7)
+#define ATA_DATA_EVEN ATA_IO_REG(8)
+#define ATA_DATA_ODD ATA_IO_REG(9)
#define ATA_STATUS ATA_COMMAND
#define ATA_DEV_CTL ATA_IO_ALT(6)
#define ATA_LBA_LOW ATA_SECT_NUM
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 020cc8312..b62095fec 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -80,17 +80,13 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#ifdef CONFIG_LCD
+#if defined(CONFIG_LCD)
# undef CONFIG_STATUS_LED /* disturbs display */
#else
# define CONFIG_STATUS_LED 1 /* Status LED enabled */
#endif /* CONFIG_LCD */
-#ifdef CONFIG_BMS2003
-# define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-#else
-# undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#endif
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
diff --git a/include/configs/bms2003.h b/include/configs/bms2003.h
new file mode 100644
index 000000000..c5d5d88d0
--- /dev/null
+++ b/include/configs/bms2003.h
@@ -0,0 +1,515 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_BMS2003
+#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
+#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+
+#define CONFIG_LCD
+#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
+
+#ifdef CONFIG_LCD /* with LCD controller ? */
+#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/TQM860L/uImage\0" \
+ "kernel_addr=40040000\0" \
+ "ramdisk_addr=40100000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+#ifdef CONFIG_SPLASH_SCREEN
+# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_BMP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE )
+#else
+# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE )
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if 0
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR \
+ ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else /* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif /* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR (/* SCCR_TBS | */ \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#else /* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+#endif /* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#ifndef CONFIG_BMS2003
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+#else /* CONFIG_BMS2003 */
+#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC100000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else /* 50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif /*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif /* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ * gclk CPU clock (not bus clock!)
+ * Trefresh Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider = 98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA 156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA 129
+#else /* 50 MHz */
+#define CFG_MAMR_PTA 98
+#endif /*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index 47f7c355a..3438bde32 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -43,7 +43,7 @@ void status_led_tick (unsigned long timestamp);
void status_led_set (int led, int state);
/***** TQM8xxL ********************************************************/
-#if defined(CONFIG_TQM8xxL)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_BMS2003)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
@@ -318,6 +318,21 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+/***** BMS2003 ********************************************************/
+#elif defined(CONFIG_BMS2003)
+# define STATUS_LED_PAR im_ioport.iop_papar
+# define STATUS_LED_DIR im_ioport.iop_padir
+# define STATUS_LED_ODR im_ioport.iop_paodr
+# define STATUS_LED_DAT im_ioport.iop_padat
+
+# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/************************************************************************/
#else
# error Status LED configuration missing