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authorstroese <stroese>2003-12-09 14:56:24 +0000
committerstroese <stroese>2003-12-09 14:56:24 +0000
commit939403bca911e8216dc13d1e029f7483aa790002 (patch)
tree3afe39aab597ae7d854e978c05cda5f3d7a0f6e7
parentb828dda657dd26b5580c4a85e5680a5d16352a4c (diff)
downloadu-boot-linaro-stable-939403bca911e8216dc13d1e029f7483aa790002.tar.gz
Updated for PPC405EP boards (2 banks only).
-rw-r--r--cpu/ppc4xx/spd_sdram.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 289ad1289..418b9da3b 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -432,9 +432,15 @@ long int spd_sdram(int(read_spd)(uint addr))
tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
sdram0_b0cr = (bank_size) * 0 | tmp;
+#ifndef CONFIG_405EP /* not on PPC405EP */
if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
+#else
+ /* PPC405EP chip only supports two SDRAM banks */
+ if(bank_cnt>1) sdram0_b1cr = (bank_size) * 1 | tmp;
+ if(bank_cnt>2) total_size -= (bank_size) * (bank_cnt - 2);
+#endif
/*
@@ -464,8 +470,10 @@ long int spd_sdram(int(read_spd)(uint addr))
mtsdram0( mem_pmit , sdram0_pmit );
mtsdram0( mem_mb0cf , sdram0_b0cr );
mtsdram0( mem_mb1cf , sdram0_b1cr );
+#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_mb2cf , sdram0_b2cr );
mtsdram0( mem_mb3cf , sdram0_b3cr );
+#endif
mtsdram0( mem_sdtr1 , sdram0_tr );
/* SDRAM have a power on delay, 500 micro should do */