aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorstroese <stroese>2003-02-18 11:30:24 +0000
committerstroese <stroese>2003-02-18 11:30:24 +0000
commit2a9e02ead3024f33658f1f4110834d0601dd6b2f (patch)
tree8a80f965ecb8fe686e020293669aa58c9ced1889
parentd7787c6e57f602d1f8c17c94886b81ee2ae229c2 (diff)
downloadu-boot-linaro-stable-2a9e02ead3024f33658f1f4110834d0601dd6b2f.tar.gz
CPCIISER4 configuration updated.
-rw-r--r--CHANGELOG3
-rw-r--r--include/configs/CPCIISER4.h15
2 files changed, 11 insertions, 7 deletions
diff --git a/CHANGELOG b/CHANGELOG
index d22ce04dd..ef7e51465 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
Changes since U-Boot 0.2.1:
======================================================================
+* Patch by Stefan Roese, 18 Feb 2003:
+ CPCIISER4 configuration updated.
+
* Patch by Stefan Roese, 17 Feb 2003:
Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 6c8d7f692..174b0e51f 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@@ -56,6 +56,7 @@
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM )
@@ -223,12 +224,12 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
+#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
+#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions