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authorJohn Rigby <john.rigby@linaro.org>2011-09-22 21:55:14 -0600
committerJohn Rigby <john.rigby@linaro.org>2012-05-02 19:44:11 -0600
commit53bb513f7363cf3a02d12e1f062313154cc752d8 (patch)
tree4bf39d21be98e288b70c1cf7e9905e3db241c507
parent92b869739c7cd51e319fb2cea1bb2e5d4c6b25ea (diff)
downloadu-boot-linaro-stable-53bb513f7363cf3a02d12e1f062313154cc752d8.tar.gz
SAUCE: HACK: move omap spl base address
Move NON_SECURE_SRAM_START from 0x40304000 to 0x40303000 and move u-boot-spl load address from 0x40304350 to 0x40303080. This allows it to stay under 0x4030c000 which is what the TRM says it must do. SRAM actually starts at 0x40300000 on GP devices but was set to 0x40304000 to be the same as Secure devices so this breaks that. Signed-off-by: John Rigby <john.rigby@linaro.org>
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h2
-rw-r--r--include/configs/omap4_common.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 416c6de31..6d1910199 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -172,7 +172,7 @@ struct control_lpddr2io_regs {
* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
* at 0x40304000(EMU base) so that our code works for both EMU and GP
*/
-#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_START 0x40303000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 003250906..3c12c0da4 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -285,7 +285,7 @@
/* Defines for SPL */
#define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE 0x40304350
+#define CONFIG_SPL_TEXT_BASE 0x40303080
#define CONFIG_SPL_MAX_SIZE (38 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK