diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2011-12-22 08:42:06 +0100 |
|---|---|---|
| committer | John Rigby <john.rigby@linaro.org> | 2012-01-19 17:08:51 -0700 |
| commit | ba5ee185ad76cb41f028e5816f7f1d0e4e5ef724 (patch) | |
| tree | eea18644bc7ad14734149a4e8c5e46c4632fedfc | |
| parent | 85fe4bf4ae2e1eed20979445030354b3e491b907 (diff) | |
mx6qsabrelite: enet: force master, maximize tx clock delay
Register 0x106 is tx data delay register.
With this patch, gigabit mode still does not work reliably.
Ping shows about a 10% packet loss on large packets.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| -rw-r--r-- | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 5c811dec6..b76146d6c 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis) int fecmxc_mii_postcall(int phy) { - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); + /* force master mode */ + miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00); /* min rx data delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + /* min tx data delay */ + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106); + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + /* max rx/tx clock delay, min rx/tx control delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); |